| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | hwinit.c | 59 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); in io_settings_lpddr2()
60 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); in io_settings_lpddr2()
61 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); in io_settings_lpddr2()
62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); in io_settings_lpddr2()
63 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_lpddr2()
64 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_lpddr2()
65 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); in io_settings_lpddr2()
66 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); in io_settings_lpddr2()
67 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); in io_settings_lpddr2()
77 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); in io_settings_ddr3()
[all …]
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| H A D | dra7xx_iodelay.c | 21 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
23 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
35 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
38 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
149 cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET, in do_set_iodelay()
154 fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET, in do_set_iodelay()
179 writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_start()
182 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
190 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
209 writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_end()
[all …]
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| /openbmc/u-boot/drivers/ddr/microchip/ |
| H A D | ddr2.c | 66 static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, in ddr_set_arbiter() argument
73 writel(i * MIN_LIM_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
74 writel(param->min_limit, &ctrl->minlim); in ddr_set_arbiter()
77 writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
78 writel(param->req_period, &ctrl->reqprd); in ddr_set_arbiter()
81 writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
82 writel(param->min_cmd_acpt, &ctrl->mincmd); in ddr_set_arbiter()
100 static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, in host_load_cmd() argument
106 writel(hostcmd1, &ctrl->cmd10[cmd_idx]); in host_load_cmd()
107 writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); in host_load_cmd()
[all …]
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | hwinit.c | 54 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); in do_io_settings()
55 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); in do_io_settings()
58 (*ctrl)->control_lpddr2io1_2); in do_io_settings()
59 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); in do_io_settings()
62 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); in do_io_settings()
63 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); in do_io_settings()
66 (*ctrl)->control_lpddr2io2_2); in do_io_settings()
67 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); in do_io_settings()
75 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { in do_io_settings()
78 (*ctrl)->control_ldosram_iva_voltage_ctrl); in do_io_settings()
[all …]
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| /openbmc/u-boot/drivers/usb/host/ |
| H A D | xhci-mem.c | 103 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl) in xhci_scratchpad_free() argument
105 if (!ctrl->scratchpad) in xhci_scratchpad_free()
108 ctrl->dcbaa->dev_context_ptrs[0] = 0; in xhci_scratchpad_free()
110 free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]); in xhci_scratchpad_free()
111 free(ctrl->scratchpad->sp_array); in xhci_scratchpad_free()
112 free(ctrl->scratchpad); in xhci_scratchpad_free()
113 ctrl->scratchpad = NULL; in xhci_scratchpad_free()
134 static void xhci_free_virt_devices(struct xhci_ctrl *ctrl) in xhci_free_virt_devices() argument
145 virt_dev = ctrl->devs[slot_id]; in xhci_free_virt_devices()
149 ctrl->dcbaa->dev_context_ptrs[slot_id] = 0; in xhci_free_virt_devices()
[all …]
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| H A D | ehci-hcd.c | 121 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) in ehci_get_port_speed() argument
126 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) in ehci_set_usbmode() argument
131 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); in ehci_set_usbmode()
142 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, in ehci_powerup_fixup() argument
148 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) in ehci_get_portsc_register() argument
150 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); in ehci_get_portsc_register()
159 return (uint32_t *)&ctrl->hcor->or_portsc[port]; in ehci_get_portsc_register()
178 static int ehci_reset(struct ehci_ctrl *ctrl) in ehci_reset() argument
183 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); in ehci_reset()
185 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); in ehci_reset()
[all …]
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| H A D | xhci-ring.c | 35 static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, in last_trb() argument
38 if (ring == ctrl->event_ring) in last_trb()
54 static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl, in last_trb_on_last_seg() argument
59 if (ring == ctrl->event_ring) in last_trb_on_last_seg()
88 static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, in inc_enq() argument
101 while (last_trb(ctrl, ring, ring->enq_seg, next)) { in inc_enq()
102 if (ring != ctrl->event_ring) { in inc_enq()
128 if (last_trb_on_last_seg(ctrl, ring, in inc_enq()
146 static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring) in inc_deq() argument
154 if (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)) { in inc_deq()
[all …]
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| H A D | xhci.c | 453 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); in xhci_configure_endpoints() local
456 virt_dev = ctrl->devs[udev->slot_id]; in xhci_configure_endpoints()
460 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0, in xhci_configure_endpoints()
462 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); in xhci_configure_endpoints()
478 xhci_acknowledge_event(ctrl); in xhci_configure_endpoints()
501 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); in xhci_set_configuration() local
506 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; in xhci_set_configuration()
537 xhci_slot_copy(ctrl, in_ctx, out_ctx); in xhci_set_configuration()
538 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); in xhci_set_configuration()
542 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); in xhci_set_configuration()
[all …]
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | fsl_elbc_nand.c | 48 struct fsl_elbc_ctrl *ctrl; member
158 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in set_addr() local
159 fsl_lbc_t *lbc = ctrl->regs; in set_addr()
162 ctrl->page = page_addr; in set_addr()
178 ctrl->addr = priv->vbase + buf_num * 1024; in set_addr()
179 ctrl->index = column; in set_addr()
183 ctrl->index += priv->page_size ? 2048 : 512; in set_addr()
187 buf_num, ctrl->addr, priv->vbase, ctrl->index, in set_addr()
198 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_run_command() local
199 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_run_command()
[all …]
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| H A D | fsl_ifc_nand.c | 34 struct fsl_ifc_ctrl *ctrl; member
225 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in set_addr() local
226 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in set_addr()
229 ctrl->page = page_addr; in set_addr()
237 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); in set_addr()
238 ctrl->index = column; in set_addr()
242 ctrl->index += mtd->writesize; in set_addr()
246 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, in check_read_ecc() argument
259 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_run_command() local
260 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in fsl_ifc_run_command()
[all …]
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| H A D | kirkwood_nand.c | 19 u32 ctrl; /* 0x10470 */ member
33 unsigned int ctrl) in kw_nand_hwcontrol() argument
41 if (ctrl & NAND_CLE) in kw_nand_hwcontrol()
43 else if (ctrl & NAND_ALE) in kw_nand_hwcontrol()
71 data = readl(&nf_reg->ctrl); in kw_nand_select_chip()
73 writel(data, &nf_reg->ctrl); in kw_nand_select_chip()
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| /openbmc/u-boot/drivers/pinctrl/rockchip/ |
| H A D | pinctrl-rockchip-core.c | 22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() local
46 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
47 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
53 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
65 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_mux_route() local
69 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
70 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
[all …]
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| /openbmc/qemu/target/riscv/ |
| H A D | debug.c | 312 target_ulong ctrl = env->tdata1[trigger_index]; in trigger_priv_match() local
321 if ((ctrl >> 3) & BIT(env->priv)) { in trigger_priv_match()
328 if ((ctrl >> 23) & BIT(env->priv)) { in trigger_priv_match()
333 if ((ctrl >> 3) & BIT(env->priv)) { in trigger_priv_match()
341 if ((ctrl >> 25) & BIT(env->priv)) { in trigger_priv_match()
346 if ((ctrl >> 6) & BIT(env->priv)) { in trigger_priv_match()
420 static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) in type2_breakpoint_size() argument
425 sizehi = extract32(ctrl, 21, 2); in type2_breakpoint_size()
427 sizelo = extract32(ctrl, 16, 2); in type2_breakpoint_size()
431 static inline bool type2_breakpoint_enabled(target_ulong ctrl) in type2_breakpoint_enabled() argument
[all …]
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| /openbmc/u-boot/arch/arm/mach-orion5x/ |
| H A D | cpu.c | 94 writel(0, &winregs[0].ctrl); in orion5x_config_adr_windows()
100 ORION5X_WIN_ENABLE), &winregs[0].ctrl); in orion5x_config_adr_windows()
102 writel(0, &winregs[1].ctrl); in orion5x_config_adr_windows()
108 ORION5X_WIN_ENABLE), &winregs[1].ctrl); in orion5x_config_adr_windows()
110 writel(0, &winregs[2].ctrl); in orion5x_config_adr_windows()
114 ORION5X_WIN_ENABLE), &winregs[2].ctrl); in orion5x_config_adr_windows()
116 writel(0, &winregs[3].ctrl); in orion5x_config_adr_windows()
120 ORION5X_WIN_ENABLE), &winregs[3].ctrl); in orion5x_config_adr_windows()
122 writel(0, &winregs[4].ctrl); in orion5x_config_adr_windows()
126 ORION5X_WIN_ENABLE), &winregs[4].ctrl); in orion5x_config_adr_windows()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/ |
| H A D | timer.c | 35 writel(GPT_CTRL_SWR, &gpt->ctrl); in timer_init()
40 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
43 writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, in timer_init()
44 &gpt->ctrl); in timer_init()
45 writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); in timer_init()
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| /openbmc/u-boot/arch/arm/cpu/arm1136/mx35/ |
| H A D | timer.c | 31 writel(GPTCR_SWR, &gpt->ctrl); in timer_init()
36 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
39 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
40 &gpt->ctrl); in timer_init()
41 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); in timer_init()
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | socfpga_gen5.c | 24 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()
44 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
59 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
75 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
78 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()
81 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
96 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
114 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_init()
148 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
196 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | devices.c | 17 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; variable
26 clrbits_le32(&ctrl->loop, in lpc32xx_uart_init()
36 clrsetbits_le32(&ctrl->clkmode, in lpc32xx_uart_init()
113 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); in lpc32xx_usb_init()
119 uint32_t ctrl = readl(&clk->i2cclk_ctrl); in lpc32xx_i2c_init() local
121 ctrl |= CLK_I2C1_ENABLE; in lpc32xx_i2c_init()
123 ctrl |= CLK_I2C2_ENABLE; in lpc32xx_i2c_init()
124 writel(ctrl, &clk->i2cclk_ctrl); in lpc32xx_i2c_init()
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| /openbmc/u-boot/drivers/net/ |
| H A D | ftmac110.c | 214 chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK); in ftmac110_reset()
221 chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK); in ftmac110_reset()
222 chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER); in ftmac110_reset()
284 uint64_t ctrl; in ftmac110_send() local
297 ctrl = le64_to_cpu(txd->ctrl); in ftmac110_send()
298 if (ctrl & FTMAC110_TXD_OWNER) { in ftmac110_send()
309 ctrl &= FTMAC110_TXD_CLRMASK; in ftmac110_send()
311 ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS; in ftmac110_send()
313 ctrl |= FTMAC110_TXD_OWNER; in ftmac110_send()
315 txd->ctrl = cpu_to_le64(ctrl); in ftmac110_send()
[all …]
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| /openbmc/u-boot/drivers/rtc/ |
| H A D | rx8010sj.c | 149 u8 ctrl[2]; in rx8010sj_rtc_init() local
174 ctrl[i] = ret; in rx8010sj_rtc_init()
177 if (ctrl[0] & RX8010_FLAG_VLF) in rx8010sj_rtc_init()
180 if (ctrl[0] & RX8010_FLAG_AF) { in rx8010sj_rtc_init()
185 if (ctrl[0] & RX8010_FLAG_TF) in rx8010sj_rtc_init()
188 if (ctrl[0] & RX8010_FLAG_UF) in rx8010sj_rtc_init()
192 ctrl[0] &= ~(RX8010_FLAG_AF | RX8010_FLAG_TF | RX8010_FLAG_UF); in rx8010sj_rtc_init()
193 ret = rx8010sj_rtc_write8(dev, RX8010_FLAG, ctrl[0]); in rx8010sj_rtc_init()
252 int ctrl, flagreg; in rx8010sj_rtc_set() local
260 ctrl = rx8010sj_rtc_read8(dev, RX8010_CTRL); in rx8010sj_rtc_set()
[all …]
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| /openbmc/u-boot/arch/arc/lib/ |
| H A D | cache.c | 275 unsigned int ctrl; in __slc_entire_op() local
280 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_entire_op()
283 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ in __slc_entire_op()
285 ctrl |= SLC_CTRL_IM; in __slc_entire_op()
287 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
323 unsigned int ctrl; in __slc_rgn_op() local
335 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_rgn_op()
339 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ in __slc_rgn_op()
341 ctrl |= SLC_CTRL_IM; in __slc_rgn_op()
344 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ in __slc_rgn_op()
[all …]
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| /openbmc/u-boot/arch/arm/mach-kirkwood/ |
| H A D | cache.c | 13 u32 ctrl; in l2_cache_disable() local
15 ctrl = readfr_extra_feature_reg(); in l2_cache_disable()
16 ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN; in l2_cache_disable()
17 writefr_extra_feature_reg(ctrl); in l2_cache_disable()
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| /openbmc/u-boot/drivers/usb/gadget/ |
| H A D | f_dfu.c | 264 const struct usb_ctrlrequest *ctrl, in state_app_idle() argument
270 switch (ctrl->bRequest) { in state_app_idle()
291 const struct usb_ctrlrequest *ctrl, in state_app_detach() argument
297 switch (ctrl->bRequest) { in state_app_detach()
314 const struct usb_ctrlrequest *ctrl, in state_dfu_idle() argument
318 u16 w_value = le16_to_cpu(ctrl->wValue); in state_dfu_idle()
319 u16 len = le16_to_cpu(ctrl->wLength); in state_dfu_idle()
322 switch (ctrl->bRequest) { in state_dfu_idle()
374 const struct usb_ctrlrequest *ctrl, in state_dfu_dnload_sync() argument
380 switch (ctrl->bRequest) { in state_dfu_dnload_sync()
[all …]
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| /openbmc/u-boot/board/xes/common/ |
| H A D | actl_nand.c | 16 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) in nand_addr_hwcontrol() argument
21 if (ctrl & NAND_CTRL_CHANGE) { in nand_addr_hwcontrol()
27 if (ctrl & NAND_CLE) in nand_addr_hwcontrol()
29 if (ctrl & NAND_ALE) in nand_addr_hwcontrol()
31 if (ctrl & NAND_NCE) in nand_addr_hwcontrol()
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| /openbmc/u-boot/drivers/video/sunxi/ |
| H A D | sunxi_dw_hdmi.c | 28 u32 ctrl; member
67 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
68 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
70 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
73 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
75 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
77 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
79 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
[all …]
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