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Searched refs:ctr_idx (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c82 static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_counter_valid() argument
84 if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || in riscv_pmu_counter_valid()
85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { in riscv_pmu_counter_valid()
92 static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_counter_enabled() argument
96 if (riscv_pmu_counter_valid(cpu, ctr_idx) && in riscv_pmu_counter_enabled()
97 !get_field(env->mcountinhibit, BIT(ctr_idx))) { in riscv_pmu_counter_enabled()
104 static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_incr_ctr_rv32() argument
108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv32()
113 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || in riscv_pmu_incr_ctr_rv32()
115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv32()
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H A Dpmu.h32 uint32_t ctr_idx);
36 uint32_t ctr_idx);
40 bool upper_half, uint32_t ctr_idx);
H A Dcsr.c1110 int ctr_idx = csrno - CSR_MCYCLE; in write_mhpmcounter() local
1111 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in write_mhpmcounter()
1115 if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && in write_mhpmcounter()
1116 (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || in write_mhpmcounter()
1117 riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { in write_mhpmcounter()
1119 ctr_idx, false); in write_mhpmcounter()
1120 if (ctr_idx > 2) { in write_mhpmcounter()
1125 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); in write_mhpmcounter()
1138 int ctr_idx = csrno - CSR_MCYCLEH; in write_mhpmcounterh() local
1139 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in write_mhpmcounterh()
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/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_pmu.c160 int ctr_idx = -1; in kvm_pmu_get_programmable_pmc_index() local
178 ctr_idx = pmc_idx; in kvm_pmu_get_programmable_pmc_index()
183 return ctr_idx; in kvm_pmu_get_programmable_pmc_index()
461 int ctr_idx, ret, sbiret = 0; in kvm_riscv_vcpu_pmu_ctr_cfg_match() local
503 ctr_idx = ctr_base + __ffs(ctr_mask); in kvm_riscv_vcpu_pmu_ctr_cfg_match()
505 ctr_idx = pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask); in kvm_riscv_vcpu_pmu_ctr_cfg_match()
506 if (ctr_idx < 0) { in kvm_riscv_vcpu_pmu_ctr_cfg_match()
512 pmc = &kvpmu->pmc[ctr_idx]; in kvm_riscv_vcpu_pmu_ctr_cfg_match()
513 pmc->idx = ctr_idx; in kvm_riscv_vcpu_pmu_ctr_cfg_match()
524 set_bit(ctr_idx, kvpmu->pmc_in_use); in kvm_riscv_vcpu_pmu_ctr_cfg_match()
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/openbmc/linux/drivers/perf/arm_cspmu/
H A Darm_cspmu.c689 static inline u32 counter_offset(u32 reg_sz, u32 ctr_idx) in counter_offset() argument
691 return (PMEVCNTR_LO + (reg_sz * ctr_idx)); in counter_offset()