862     int ctr_idx = csrno - CSR_MCYCLE;  in write_mhpmcounter()  local
863     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in write_mhpmcounter()
867     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||  in write_mhpmcounter()
868         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {  in write_mhpmcounter()
870         if (ctr_idx > 2) {  in write_mhpmcounter()
875             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);  in write_mhpmcounter()
887     int ctr_idx = csrno - CSR_MCYCLEH;  in write_mhpmcounterh()  local
888     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in write_mhpmcounterh()
894     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||  in write_mhpmcounterh()
895         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {  in write_mhpmcounterh()
897         if (ctr_idx > 2) {  in write_mhpmcounterh()
898             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);  in write_mhpmcounterh()
908                                          bool upper_half, uint32_t ctr_idx)  in riscv_pmu_read_ctr()  argument
910     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in riscv_pmu_read_ctr()
916     if (get_field(env->mcountinhibit, BIT(ctr_idx))) {  in riscv_pmu_read_ctr()
935     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||  in riscv_pmu_read_ctr()
936         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {  in riscv_pmu_read_ctr()