| /openbmc/linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_gen4_hw_data.h | 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
29 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
33 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
40 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
45 void __iomem *_csr_base_addr = csr_base_addr; \
61 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
68 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
[all …]
|
| H A D | adf_gen2_hw_data.h | 31 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
63 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
70 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
[all …]
|
| H A D | adf_gen4_hw_data.c | 15 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
21 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
26 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
32 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
37 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
49 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); in write_csr_ring_base()
55 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); in write_csr_int_flag()
60 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); in write_csr_int_srcsel()
65 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); in write_csr_int_col_en()
71 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); in write_csr_int_col_ctl()
[all …]
|
| H A D | adf_gen2_hw_data.c | 121 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
127 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
132 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
138 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
143 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
155 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); in write_csr_ring_base()
160 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); in write_csr_int_flag()
165 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); in write_csr_int_srcsel()
171 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); in write_csr_int_col_en()
177 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); in write_csr_int_col_ctl()
[all …]
|
| H A D | adf_accel_devices.h | 124 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
126 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
128 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
130 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
132 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
133 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
135 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
137 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
139 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
140 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
[all …]
|