28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \  argument
29 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \  argument
33 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \  argument
37 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \  argument
40 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value)	\  argument
45 	void __iomem *_csr_base_addr = csr_base_addr; \
60 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \  argument
61 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
64 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \  argument
65 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
68 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \  argument
69 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
72 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \  argument
73 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
76 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \  argument
77 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
80 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \  argument
81 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
85 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \  argument
86 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
93 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \  argument
94 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \