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Searched refs:cs_count (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dxor.c23 u32 reg, ui, cs_count; in mv_sys_xor_init() local
35 for (ui = 0, cs_count = 0; in mv_sys_xor_init()
36 (cs_count < num_of_cs) && (ui < 8); in mv_sys_xor_init()
37 ui++, cs_count++) { in mv_sys_xor_init()
48 cs_count = 0; in mv_sys_xor_init()
49 for (ui = 0, cs_count = 0; in mv_sys_xor_init()
50 (cs_count < num_of_cs) && (ui < 8); in mv_sys_xor_init()
51 ui++, cs_count++) { in mv_sys_xor_init()
/openbmc/qemu/hw/ssi/
H A Dnpcm7xx_fiu.c111 g_assert(index >= 0 && index < fiu->cs_count); in npcm7xx_fiu_cs_index()
121 if (cs_id < s->cs_count) { in npcm7xx_fiu_select()
127 DEVICE(s)->canonical_path, cs_id, s->cs_count); in npcm7xx_fiu_select()
493 for (i = 0; i < s->cs_count; i++) { in npcm7xx_fiu_hold_reset()
504 if (s->cs_count <= 0) { in npcm7xx_fiu_realize()
506 dev->canonical_path, s->cs_count); in npcm7xx_fiu_realize()
522 s->cs_lines = g_new0(qemu_irq, s->cs_count); in npcm7xx_fiu_realize()
523 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count); in npcm7xx_fiu_realize()
524 s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count); in npcm7xx_fiu_realize()
534 for (i = 0; i < s->cs_count; i++) { in npcm7xx_fiu_realize()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c585 __maybe_unused u32 dimm_cnt, cs_count, dimm; local
894 cs_count = 0;
898 if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) {
900 cs_count = 0;
902 cs_count++;
918 cs_count = 0;
922 if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) {
924 cs_count = 0;
926 cs_count++;
1011 cs_count = 0;
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H A Dxor.c25 u32 reg, ui, base, cs_count; in mv_sys_xor_init() local
49 cs_count = 0; in mv_sys_xor_init()
71 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
74 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
75 cs_count++; in mv_sys_xor_init()
H A Dddr3_dqs.c310 u32 uj, cs_count, cs_tmp, ii; in ddr3_find_adll_limits() local
332 cs_count = 0; in ddr3_find_adll_limits()
335 cs_count++; in ddr3_find_adll_limits()
337 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1); in ddr3_find_adll_limits()
1329 u32 cs, cs_count, cs_tmp, victim_dq; in ddr3_load_dqs_patterns() local
1336 cs_count = 0; in ddr3_load_dqs_patterns()
1339 cs_count++; in ddr3_load_dqs_patterns()
1343 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
1358 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
H A Dddr3_pbs.c1532 u32 cs, cs_count, cs_tmp; in ddr3_load_pbs_patterns() local
1561 cs_count = 0; in ddr3_load_pbs_patterns()
1564 cs_count++; in ddr3_load_pbs_patterns()
1568 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
1578 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
H A Dddr3_init.c1073 u32 cs_count = 0; in ddr3_get_cs_num_from_reg() local
1078 cs_count++; in ddr3_get_cs_num_from_reg()
1081 return cs_count; in ddr3_get_cs_num_from_reg()
/openbmc/qemu/include/hw/ssi/
H A Dnpcm7xx_fiu.h60 int32_t cs_count; member
/openbmc/qemu/hw/arm/
H A Dnpcm8xx.c334 int cs_count; member
341 .cs_count = ARRAY_SIZE(npcm8xx_fiu0_flash_addr),
348 .cs_count = ARRAY_SIZE(npcm8xx_fiu1_flash_addr),
354 .cs_count = ARRAY_SIZE(npcm8xx_fiu3_flash_addr),
731 npcm8xx_fiu[i].cs_count, &error_abort); in npcm8xx_realize()
737 for (j = 0; j < npcm8xx_fiu[i].cs_count; j++) { in npcm8xx_realize()
H A Dnpcm7xx.c293 int cs_count; member
300 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
307 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
741 npcm7xx_fiu[i].cs_count, &error_abort); in npcm7xx_realize()
747 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { in npcm7xx_realize()