Searched refs:crc_pll (Results 1 – 6 of 6) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 81 return &clkrst->crc_pll[clkid]; in get_pll()
793 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
799 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
804 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
810 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 944 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
948 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
953 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
959 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
1015 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1023 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
1029 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | clock.c | 665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
709 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot_avp.c | 202 writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); in wb_start()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 845 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
878 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
882 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
889 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clk_rst.h | 77 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ member
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