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Searched refs:cpu_reg (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-main.c105 cpu_reg(host_ctxt, 1) = ret; in handle___kvm_vcpu_run()
164 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); in handle___kvm_timer_set_cntvoff()
178 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); in handle___vgic_v3_get_gic_config()
183 cpu_reg(host_ctxt, 1) = __vgic_v3_read_vmcr(); in handle___vgic_v3_read_vmcr()
188 __vgic_v3_write_vmcr(cpu_reg(host_ctxt, 1)); in handle___vgic_v3_write_vmcr()
198 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); in handle___kvm_get_mdcr_el2()
228 cpu_reg(host_ctxt, 1) = __pkvm_init(phys, size, nr_cpus, per_cpu_base, in handle___pkvm_init()
236 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); in handle___pkvm_cpu_set_vector()
243 cpu_reg(host_ctxt, 1) = __pkvm_host_share_hyp(pfn); in handle___pkvm_host_share_hyp()
250 cpu_reg(host_ctxt, 1) = __pkvm_host_unshare_hyp(pfn); in handle___pkvm_host_unshare_hyp()
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H A Dpsci-relay.c74 return psci_call(cpu_reg(host_ctxt, 0), cpu_reg(host_ctxt, 1), in psci_forward()
75 cpu_reg(host_ctxt, 2), cpu_reg(host_ctxt, 3)); in psci_forward()
215 cpu_reg(host_ctxt, 0) = boot_args->r0; in __kvm_host_psci_cpu_entry()
298 cpu_reg(host_ctxt, 0) = ret; in kvm_host_psci_handler()
299 cpu_reg(host_ctxt, 1) = 0; in kvm_host_psci_handler()
300 cpu_reg(host_ctxt, 2) = 0; in kvm_host_psci_handler()
301 cpu_reg(host_ctxt, 3) = 0; in kvm_host_psci_handler()
H A Dffa.c97 cpu_reg(ctxt, 0) = res->a0; in ffa_set_retval()
98 cpu_reg(ctxt, 1) = res->a1; in ffa_set_retval()
99 cpu_reg(ctxt, 2) = res->a2; in ffa_set_retval()
100 cpu_reg(ctxt, 3) = res->a3; in ffa_set_retval()
H A Dsetup.c309 cpu_reg(host_ctxt, 1) = ret; in __pkvm_init_finalise()
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbnx2_fw.h12 static const struct cpu_reg cpu_reg_com = {
28 static const struct cpu_reg cpu_reg_cp = {
44 static const struct cpu_reg cpu_reg_rxp = {
60 static const struct cpu_reg cpu_reg_tpat = {
76 static const struct cpu_reg cpu_reg_txp = {
H A Dbnx2.c3831 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, in load_cpu_fw() argument
3840 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); in load_cpu_fw()
3841 val |= cpu_reg->mode_value_halt; in load_cpu_fw()
3842 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3843 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3851 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3865 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3879 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3888 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3891 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); in load_cpu_fw()
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H A Dbnx2.h7015 struct cpu_reg { struct
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a64.c538 TCGv_i64 cpu_reg(DisasContext *s, int reg) in cpu_reg() function
1459 gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); in trans_BL()
1489 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, a->rt), 1ULL << a->bitpos); in trans_TBZ()
1549 gen_a64_set_pc(s, cpu_reg(s, a->rn)); in trans_BR()
1556 TCGv_i64 dst = cpu_reg(s, a->rn); in trans_BLR()
1557 TCGv_i64 lr = cpu_reg(s, 30); in trans_BLR()
1572 gen_a64_set_pc(s, cpu_reg(s, a->rn)); in trans_RET()
1607 dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); in trans_BRAZ()
1622 dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); in trans_BLRAZ()
1623 lr = cpu_reg( in trans_BLRAZ()
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H A Dtranslate-sme.c46 tcg_gen_trunc_tl_i32(tmp, cpu_reg(s, rs)); in get_tile_rowcol()
232 tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); in trans_LDST1()
H A Dtranslate-a64.h21 TCGv_i64 cpu_reg(DisasContext *s, int reg);
H A Dtranslate-sve.c1127 tcg_constant_i64(a->imm), cpu_reg(s, a->rm))
1129 cpu_reg(s, a->rn), tcg_constant_i64(a->imm))
1131 cpu_reg(s, a->rn), cpu_reg(s, a->rm))
1195 TCGv_i64 reg = cpu_reg(s, a->rd); in trans_RDVL()
1207 TCGv_i64 reg = cpu_reg(s, a->rd); in trans_RDSVL()
1888 tcg_gen_movi_i64(cpu_reg(s, a->rd), numelem * a->imm); in trans_CNT_r()
1902 TCGv_i64 reg = cpu_reg(s, a->rd); in trans_INCDEC_r()
1921 TCGv_i64 reg = cpu_reg(s, a->rd); in trans_SINCDEC_r_32()
1948 TCGv_i64 reg = cpu_reg(s, a->rd); in trans_SINCDEC_r_64()
2230 do_insr_i64(s, a, cpu_reg(s, a->rm)); in trans_INSR_r()
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/openbmc/linux/arch/arm64/kvm/hyp/include/nvhe/
H A Dtrap_handler.h14 #define cpu_reg(ctxt, r) (ctxt)->regs.regs[r] macro
16 type name = (type)cpu_reg(ctxt, (reg))
/openbmc/linux/drivers/cpufreq/
H A Dmediatek-cpufreq-hw.c306 struct regulator *cpu_reg; in mtk_cpufreq_hw_driver_probe() local
315 cpu_reg = devm_regulator_get(cpu_dev, "cpu"); in mtk_cpufreq_hw_driver_probe()
316 if (IS_ERR(cpu_reg)) in mtk_cpufreq_hw_driver_probe()
317 return dev_err_probe(&pdev->dev, PTR_ERR(cpu_reg), in mtk_cpufreq_hw_driver_probe()
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra20-cpufreq.txt30 cpu_reg: regulator0 {
53 cpu-supply = <&cpu_reg>;