113857b38SDmitry OsipenkoBinding for NVIDIA Tegra20 CPUFreq
213857b38SDmitry Osipenko==================================
313857b38SDmitry Osipenko
413857b38SDmitry OsipenkoRequired properties:
513857b38SDmitry Osipenko- clocks: Must contain an entry for the CPU clock.
613857b38SDmitry Osipenko  See ../clocks/clock-bindings.txt for details.
7*94274f20SRob Herring- operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8cff1d293SAmit Kucheria- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
913857b38SDmitry Osipenko
1013857b38SDmitry OsipenkoFor each opp entry in 'operating-points-v2' table:
1113857b38SDmitry Osipenko- opp-supported-hw: Two bitfields indicating:
1213857b38SDmitry Osipenko	On Tegra20:
1313857b38SDmitry Osipenko	1. CPU process ID mask
1413857b38SDmitry Osipenko	2. SoC speedo ID mask
1513857b38SDmitry Osipenko
1613857b38SDmitry Osipenko	On Tegra30:
1713857b38SDmitry Osipenko	1. CPU process ID mask
1813857b38SDmitry Osipenko	2. CPU speedo ID mask
1913857b38SDmitry Osipenko
2013857b38SDmitry Osipenko	A bitwise AND is performed against these values and if any bit
2113857b38SDmitry Osipenko	matches, the OPP gets enabled.
2213857b38SDmitry Osipenko
2313857b38SDmitry Osipenko- opp-microvolt: CPU voltage triplet.
2413857b38SDmitry Osipenko
2513857b38SDmitry OsipenkoOptional properties:
2613857b38SDmitry Osipenko- cpu-supply: Phandle to the CPU power supply.
2713857b38SDmitry Osipenko
2813857b38SDmitry OsipenkoExample:
2913857b38SDmitry Osipenko	regulators {
3013857b38SDmitry Osipenko		cpu_reg: regulator0 {
3113857b38SDmitry Osipenko			regulator-name = "vdd_cpu";
3213857b38SDmitry Osipenko		};
3313857b38SDmitry Osipenko	};
3413857b38SDmitry Osipenko
3513857b38SDmitry Osipenko	cpu0_opp_table: opp_table0 {
3613857b38SDmitry Osipenko		compatible = "operating-points-v2";
3713857b38SDmitry Osipenko
3813857b38SDmitry Osipenko		opp@456000000 {
3913857b38SDmitry Osipenko			clock-latency-ns = <125000>;
4013857b38SDmitry Osipenko			opp-microvolt = <825000 825000 1125000>;
4113857b38SDmitry Osipenko			opp-supported-hw = <0x03 0x0001>;
4213857b38SDmitry Osipenko			opp-hz = /bits/ 64 <456000000>;
4313857b38SDmitry Osipenko		};
4413857b38SDmitry Osipenko
4513857b38SDmitry Osipenko		...
4613857b38SDmitry Osipenko	};
4713857b38SDmitry Osipenko
4813857b38SDmitry Osipenko	cpus {
4913857b38SDmitry Osipenko		cpu@0 {
5013857b38SDmitry Osipenko			compatible = "arm,cortex-a9";
5113857b38SDmitry Osipenko			clocks = <&tegra_car TEGRA20_CLK_CCLK>;
5213857b38SDmitry Osipenko			operating-points-v2 = <&cpu0_opp_table>;
5313857b38SDmitry Osipenko			cpu-supply = <&cpu_reg>;
5413857b38SDmitry Osipenko			#cooling-cells = <2>;
5513857b38SDmitry Osipenko		};
5613857b38SDmitry Osipenko	};
57