| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /openbmc/linux/drivers/clk/pxa/ |
| H A D | clk-pxa.c | 221 rate = freqs[i].cpll; in pxa2xx_determine_rate()
239 rate = freqs[closest_below].cpll; in pxa2xx_determine_rate()
241 rate = freqs[closest_above].cpll; in pxa2xx_determine_rate()
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| H A D | clk-pxa.h | 137 unsigned long cpll; member
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| H A D | clk-pxa25x.c | 244 if (pxa25x_freqs[i].cpll == rate) in clk_pxa25x_cpll_set_rate()
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| H A D | clk-pxa27x.c | 235 if (pxa27x_freqs[i].cpll == rate) in clk_pxa27x_cpll_set_rate()
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 64 apll, cpll, epll, mpll, enumerator
245 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| H A D | clk-exynos5250.c | 108 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
744 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| H A D | clk-exynos5420.c | 153 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1467 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 132 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
148 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
152 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 19 apll, cpll, dpll, gpll, enumerator
220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| H A D | clk-rk3128.c | 18 apll, dpll, cpll, gpll, enumerator
163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| H A D | clk-rk3228.c | 19 apll, dpll, cpll, gpll, enumerator
173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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| H A D | clk-rk3328.c | 21 apll, dpll, cpll, gpll, npll, enumerator
221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| H A D | clk-rk3368.c | 17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
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| H A D | clk-rk3288.c | 24 apll, dpll, cpll, gpll, npll, enumerator
230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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| H A D | clk-px30.c | 18 apll, dpll, cpll, npll, apll_b_h, apll_b_l, enumerator
191 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| H A D | clk-rv1126.c | 28 apll, dpll, cpll, hpll, enumerator
203 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| H A D | clk-rk3399.c | 19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
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| H A D | clk-rk3568.c | 23 apll, dpll, gpll, cpll, npll, vpll, enumerator
329 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| H A D | clk-rk3588.c | 41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
683 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328.dtsi | 797 * We need set cpll child clk div first,
798 * and then set the cpll frequency.
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