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Searched refs:cp15 (Results 1 – 25 of 40) sorted by relevance

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/openbmc/qemu/target/arm/
H A Ddebug_helper.c30 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || in arm_debug_target_el()
31 env->cp15.mdcr_el2 & MDCR_TDE; in arm_debug_target_el()
76 && extract32(env->cp15.mdcr_el3, 16, 1)) { in aa64_generate_debug_exceptions()
87 return extract32(env->cp15.mdscr_el1, 13, 1) in aa64_generate_debug_exceptions()
106 if (el == 0 && (env->cp15.sder & 1)) { in aa32_generate_debug_exceptions()
115 spd = extract32(env->cp15.mdcr_el3, 14, 2); in aa32_generate_debug_exceptions()
151 if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { in arm_generate_debug_exceptions()
167 return extract32(env->cp15.mdscr_el1, 0, 1) in arm_singlestep_active()
176 uint64_t bcr = env->cp15 in linked_bp_matches()
[all...]
H A Dhelper.c307 if (env->cp15.scr_el3 & SCR_EEL2) { in access_trap_aa32s_el1()
329 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in access_tpm()
636 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
641 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
656 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
662 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
676 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
677 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
718 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
721 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15
[all...]
H A Dcpu.c268 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; in arm_cpu_reset_hold()
270 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | in arm_cpu_reset_hold()
273 env->cp15.sctlr_el[1] |= SCTLR_BT0; in arm_cpu_reset_hold()
276 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; in arm_cpu_reset_hold()
279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
289 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; in arm_cpu_reset_hold()
290 env->cp15 in arm_cpu_reset_hold()
[all...]
H A Dptw.c197 s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); in ptw_idx_for_stage_2()
199 s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); in ptw_idx_for_stage_2()
216 return env->cp15.vttbr_el2; in regime_ttbr()
219 return env->cp15.vsttbr_el2; in regime_ttbr()
222 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; in regime_ttbr()
224 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; in regime_ttbr()
314 uint64_t gpccr = env->cp15.gpccr_el3; in granule_protection_check()
387 tableaddr = env->cp15.gptbr_el3 << 12; in granule_protection_check()
1044 dacr = env->cp15.dacr_ns; in get_phys_addr_v5()
1046 dacr = env->cp15.dacr_s; in get_phys_addr_v5()
[all …]
H A Dinternals.h464 uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled()
975 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; in regime_sctlr()
992 return env->cp15.vtcr_el2; in regime_tcr()
1003 uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; in regime_tcr()
1004 v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; in regime_tcr()
1007 return env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr()
1373 && !(env->cp15.scr_el3 & SCR_ATA)) { in allocation_tag_access_enabled()
1733 return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; in arm_mdcr_el2_eff()
1758 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); in arm_fgt_active()
H A Dcpu.h142 /* CPU state for each instance of a generic timer (in cp15 c14) */
267 /* System control coprocessor (cp15) */
527 } cp15;
2416 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2419 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2423 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2427 ARM_FEATURE_CBAR, /* has cp15 CBAR */
2428 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2433 ARM_FEATURE_VBAR, /* has cp15 VBAR */
2548 && (space != ARMSS_Secure || (env->cp15
526 } cp15; global() member
[all...]
/openbmc/qemu/bsd-user/arm/
H A Dtarget_arch_cpu.c26 env->cp15.tpidrurw_s = newtls; in target_cpu_set_tls()
27 env->cp15.tpidruro_s = newtls; in target_cpu_set_tls()
31 env->cp15.tpidr_el[0] = newtls; in target_cpu_set_tls()
32 env->cp15.tpidrro_el[0] = newtls; in target_cpu_set_tls()
38 return env->cp15.tpidruro_s; in target_cpu_get_tls()
40 return env->cp15.tpidrro_el[0]; in target_cpu_get_tls()
/openbmc/qemu/target/arm/hvf/
H A Dhvf.c1285 *val = env->cp15.c9_pmcr; in hvf_sysreg_read()
1289 *val = env->cp15.c15_ccnt; in hvf_sysreg_read()
1293 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1296 *val = env->cp15.c9_pmovsr; in hvf_sysreg_read()
1299 *val = env->cp15.c9_pmselr; in hvf_sysreg_read()
1302 *val = env->cp15.c9_pminten; in hvf_sysreg_read()
1305 *val = env->cp15.pmccfiltr_el0; in hvf_sysreg_read()
1308 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1311 *val = env->cp15.c9_pmuserenr; in hvf_sysreg_read()
1327 *val = env->cp15 in hvf_sysreg_read()
[all...]
/openbmc/qemu/linux-user/arm/
H A Dtarget_cpu.h60 env->cp15.tpidruro_s = newtls; in cpu_set_tls()
62 env->cp15.tpidrro_el[0] = newtls; in cpu_set_tls()
69 return env->cp15.tpidruro_s; in cpu_get_tls()
71 return env->cp15.tpidrro_el[0]; in cpu_get_tls()
H A Dcpu_loop.c532 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs()
534 env->cp15.sctlr_el[1] |= SCTLR_B; in target_cpu_copy_regs()
/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c305 if (env->cp15.hstr_el2 & HSTR_TJDBX) { in HELPER()
358 if (env->cp15.scr_el3 & mask) { in check_wfx_trap()
771 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { in HELPER()
810 if (env->cp15.hstr_el2 & mask) { in HELPER()
829 assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); in HELPER()
830 trapword = env->cp15.fgt_exec[idx]; in HELPER()
832 assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); in HELPER()
833 trapword = env->cp15.fgt_read[idx]; in HELPER()
835 assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); in HELPER()
836 trapword = env->cp15 in HELPER()
[all...]
H A Dtlb_helper.c139 ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; in report_as_gpc_exception()
206 env->cp15.mfar_el3 = fi->paddr; in arm_deliver_fault()
211 env->cp15.mfar_el3 |= R_MFAR_NS_MASK; in arm_deliver_fault()
214 env->cp15.mfar_el3 |= R_MFAR_NSE_MASK; in arm_deliver_fault()
217 env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK; in arm_deliver_fault()
236 env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; in arm_deliver_fault()
238 env->cp15.hpfar_el2 |= HPFAR_NS; in arm_deliver_fault()
H A Dhflags.c25 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : in fgt_svc()
26 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); in fgt_svc()
171 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && in rebuild_hflags_a32()
195 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) in rebuild_hflags_a32()
313 if (env->cp15.hcr_el2 & HCR_TGE) { in rebuild_hflags_a64()
328 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { in rebuild_hflags_a64()
351 if (env->cp15.sctlr_el[2] & SCTLR_EE) { in rebuild_hflags_a64()
H A Dmte_helper.c203 uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); in HELPER()
204 int rrnd = extract32(env->cp15.gcr_el1, 16, 1); in HELPER()
205 int start = extract32(env->cp15.rgsr_el1, 0, 4); in HELPER()
206 int seed = extract32(env->cp15.rgsr_el1, 8, 16); in HELPER()
244 env->cp15.rgsr_el1 = rtag | (seed << 8); in HELPER()
253 uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); in HELPER()
579 env->cp15.tfsr_el[el] |= 1 << select; in mte_async_check_fail()
602 sctlr = env->cp15.sctlr_el[reg_el]; in mte_check_fail()
/openbmc/qemu/bsd-user/aarch64/
H A Dtarget_arch_cpu.c25 env->cp15.tpidr_el[0] = newtls; in target_cpu_set_tls()
30 return env->cp15.tpidr_el[0]; in target_cpu_get_tls()
/openbmc/qemu/linux-user/aarch64/
H A Dmte_user_helper.c34 env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); in arm_set_mte_tcf0()
H A Dtarget_prctl.h184 env->cp15.gcr_el1 = in do_prctl_set_tagged_addr_ctrl()
185 deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); in do_prctl_set_tagged_addr_ctrl()
202 ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; in do_prctl_get_tagged_addr_ctrl()
203 ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); in do_prctl_get_tagged_addr_ctrl()
H A Dtarget_cpu.h41 env->cp15.tpidr_el[0] = newtls; in cpu_set_tls()
43 env->cp15.tpidr2_el0 = 0; in cpu_set_tls()
H A Dcpu_loop.c175 if (unlikely(env->cp15.tfsr_el[0])) { in cpu_loop()
176 env->cp15.tfsr_el[0] = 0; in cpu_loop()
208 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs()
210 env->cp15.sctlr_el[i] |= SCTLR_EE; in target_cpu_copy_regs()
/openbmc/linux/arch/arm/mach-exynos/
H A Dsleep.S122 .long 0 @ cp15 diagnostic
125 .long 0 @ cp15 power control
/openbmc/u-boot/arch/arm/lib/
H A DMakefile64 obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
85 CFLAGS_cache-cp15.o := -marm
/openbmc/u-boot/arch/arm/cpu/armv7/
H A DMakefile10 obj-y += cpu.o cp15.o
/openbmc/qemu/hw/arm/
H A Dboot.c701 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; in do_cpu_reset()
703 env->cp15.sctlr_el[i] &= ~SCTLR_EE; in do_cpu_reset()
708 env->cp15.sctlr_el[1] |= SCTLR_E0E; in do_cpu_reset()
710 env->cp15.sctlr_el[i] |= SCTLR_EE; in do_cpu_reset()
715 env->cp15.sctlr_el[1] |= SCTLR_B; in do_cpu_reset()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c816 bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; in icv_iar_read()
1114 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_read()
1143 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_write()
1302 if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { in icc_iar1_read()
1920 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; in icc_dir_write()
1921 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; in icc_dir_write()
1980 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { in icc_rpr_read()
2282 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { in gicv3_irqfiq_access()
2345 if (env->cp15.scr_el3 & SCR_FIQ) { in gicv3_fiq_access()
2381 if (env->cp15 in gicv3_irq_access()
[all...]
/openbmc/linux/arch/csky/abiv1/inc/abi/
H A Dentry.h160 cpseti cp15

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