1081860b9SGuo Ren /* SPDX-License-Identifier: GPL-2.0 */ 2081860b9SGuo Ren 3081860b9SGuo Ren #ifndef __ASM_CSKY_ENTRY_H 4081860b9SGuo Ren #define __ASM_CSKY_ENTRY_H 5081860b9SGuo Ren 6081860b9SGuo Ren #include <asm/setup.h> 7081860b9SGuo Ren #include <abi/regdef.h> 8081860b9SGuo Ren 9081860b9SGuo Ren #define LSAVE_PC 8 10081860b9SGuo Ren #define LSAVE_PSR 12 11081860b9SGuo Ren #define LSAVE_A0 24 12081860b9SGuo Ren #define LSAVE_A1 28 13081860b9SGuo Ren #define LSAVE_A2 32 14081860b9SGuo Ren #define LSAVE_A3 36 15081860b9SGuo Ren #define LSAVE_A4 40 16081860b9SGuo Ren #define LSAVE_A5 44 17081860b9SGuo Ren 18f8e17c17SGuo Ren #define usp ss1 19f8e17c17SGuo Ren 20081860b9SGuo Ren .macro USPTOKSP 21f8e17c17SGuo Ren mtcr sp, usp 22081860b9SGuo Ren mfcr sp, ss0 23081860b9SGuo Ren .endm 24081860b9SGuo Ren 25081860b9SGuo Ren .macro KSPTOUSP 26081860b9SGuo Ren mtcr sp, ss0 27f8e17c17SGuo Ren mfcr sp, usp 28081860b9SGuo Ren .endm 29081860b9SGuo Ren 30081860b9SGuo Ren .macro SAVE_ALL epc_inc 31081860b9SGuo Ren mtcr r13, ss2 32081860b9SGuo Ren mfcr r13, epsr 33081860b9SGuo Ren btsti r13, 31 34081860b9SGuo Ren bt 1f 35081860b9SGuo Ren USPTOKSP 36081860b9SGuo Ren 1: 37081860b9SGuo Ren subi sp, 32 38081860b9SGuo Ren subi sp, 32 39081860b9SGuo Ren subi sp, 16 40081860b9SGuo Ren stw r13, (sp, 12) 41081860b9SGuo Ren 42081860b9SGuo Ren stw lr, (sp, 4) 43081860b9SGuo Ren 44081860b9SGuo Ren mfcr lr, epc 45081860b9SGuo Ren movi r13, \epc_inc 46081860b9SGuo Ren add lr, r13 47081860b9SGuo Ren stw lr, (sp, 8) 48081860b9SGuo Ren 49f8e17c17SGuo Ren mov lr, sp 50f8e17c17SGuo Ren addi lr, 32 51f8e17c17SGuo Ren addi lr, 32 52f8e17c17SGuo Ren addi lr, 16 53f8e17c17SGuo Ren bt 2f 54081860b9SGuo Ren mfcr lr, ss1 55f8e17c17SGuo Ren 2: 56081860b9SGuo Ren stw lr, (sp, 16) 57081860b9SGuo Ren 58081860b9SGuo Ren stw a0, (sp, 20) 59081860b9SGuo Ren stw a0, (sp, 24) 60081860b9SGuo Ren stw a1, (sp, 28) 61081860b9SGuo Ren stw a2, (sp, 32) 62081860b9SGuo Ren stw a3, (sp, 36) 63081860b9SGuo Ren 64081860b9SGuo Ren addi sp, 32 65081860b9SGuo Ren addi sp, 8 66081860b9SGuo Ren mfcr r13, ss2 67081860b9SGuo Ren stw r6, (sp) 68081860b9SGuo Ren stw r7, (sp, 4) 69081860b9SGuo Ren stw r8, (sp, 8) 70081860b9SGuo Ren stw r9, (sp, 12) 71081860b9SGuo Ren stw r10, (sp, 16) 72081860b9SGuo Ren stw r11, (sp, 20) 73081860b9SGuo Ren stw r12, (sp, 24) 74081860b9SGuo Ren stw r13, (sp, 28) 75081860b9SGuo Ren stw r14, (sp, 32) 76081860b9SGuo Ren stw r1, (sp, 36) 77081860b9SGuo Ren subi sp, 32 78081860b9SGuo Ren subi sp, 8 79081860b9SGuo Ren .endm 80081860b9SGuo Ren 81081860b9SGuo Ren .macro RESTORE_ALL 82081860b9SGuo Ren ldw lr, (sp, 4) 83081860b9SGuo Ren ldw a0, (sp, 8) 84081860b9SGuo Ren mtcr a0, epc 85081860b9SGuo Ren ldw a0, (sp, 12) 86081860b9SGuo Ren mtcr a0, epsr 87081860b9SGuo Ren btsti a0, 31 88f8e17c17SGuo Ren bt 1f 89081860b9SGuo Ren ldw a0, (sp, 16) 90081860b9SGuo Ren mtcr a0, ss1 91f8e17c17SGuo Ren 1: 92081860b9SGuo Ren ldw a0, (sp, 24) 93081860b9SGuo Ren ldw a1, (sp, 28) 94081860b9SGuo Ren ldw a2, (sp, 32) 95081860b9SGuo Ren ldw a3, (sp, 36) 96081860b9SGuo Ren 97081860b9SGuo Ren addi sp, 32 98081860b9SGuo Ren addi sp, 8 99081860b9SGuo Ren ldw r6, (sp) 100081860b9SGuo Ren ldw r7, (sp, 4) 101081860b9SGuo Ren ldw r8, (sp, 8) 102081860b9SGuo Ren ldw r9, (sp, 12) 103081860b9SGuo Ren ldw r10, (sp, 16) 104081860b9SGuo Ren ldw r11, (sp, 20) 105081860b9SGuo Ren ldw r12, (sp, 24) 106081860b9SGuo Ren ldw r13, (sp, 28) 107081860b9SGuo Ren ldw r14, (sp, 32) 108081860b9SGuo Ren ldw r1, (sp, 36) 109081860b9SGuo Ren addi sp, 32 110081860b9SGuo Ren addi sp, 8 111081860b9SGuo Ren 112f8e17c17SGuo Ren bt 2f 113081860b9SGuo Ren KSPTOUSP 114f8e17c17SGuo Ren 2: 115081860b9SGuo Ren rte 116081860b9SGuo Ren .endm 117081860b9SGuo Ren 118081860b9SGuo Ren .macro SAVE_SWITCH_STACK 119081860b9SGuo Ren subi sp, 32 120081860b9SGuo Ren stm r8-r15, (sp) 121081860b9SGuo Ren .endm 122081860b9SGuo Ren 123081860b9SGuo Ren .macro RESTORE_SWITCH_STACK 124081860b9SGuo Ren ldm r8-r15, (sp) 125081860b9SGuo Ren addi sp, 32 126081860b9SGuo Ren .endm 127081860b9SGuo Ren 128081860b9SGuo Ren /* MMU registers operators. */ 129081860b9SGuo Ren .macro RD_MIR rx 130081860b9SGuo Ren cprcr \rx, cpcr0 131081860b9SGuo Ren .endm 132081860b9SGuo Ren 133081860b9SGuo Ren .macro RD_MEH rx 134081860b9SGuo Ren cprcr \rx, cpcr4 135081860b9SGuo Ren .endm 136081860b9SGuo Ren 137081860b9SGuo Ren .macro RD_MCIR rx 138081860b9SGuo Ren cprcr \rx, cpcr8 139081860b9SGuo Ren .endm 140081860b9SGuo Ren 141081860b9SGuo Ren .macro RD_PGDR rx 142081860b9SGuo Ren cprcr \rx, cpcr29 143081860b9SGuo Ren .endm 144081860b9SGuo Ren 145081860b9SGuo Ren .macro WR_MEH rx 146081860b9SGuo Ren cpwcr \rx, cpcr4 147081860b9SGuo Ren .endm 148081860b9SGuo Ren 149081860b9SGuo Ren .macro WR_MCIR rx 150081860b9SGuo Ren cpwcr \rx, cpcr8 151081860b9SGuo Ren .endm 152081860b9SGuo Ren 153205353faSGuo Ren .macro SETUP_MMU 154205353faSGuo Ren /* Init psr and enable ee */ 155205353faSGuo Ren lrw r6, DEFAULT_PSR_VALUE 156205353faSGuo Ren mtcr r6, psr 157205353faSGuo Ren psrset ee 158205353faSGuo Ren 159f62e3162SGuo Ren /* Select MMU as co-processor */ 160f62e3162SGuo Ren cpseti cp15 161f62e3162SGuo Ren 162f62e3162SGuo Ren /* 163f62e3162SGuo Ren * cpcr30 format: 164f62e3162SGuo Ren * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0 165f62e3162SGuo Ren * BA Reserved C D V 166f62e3162SGuo Ren */ 167205353faSGuo Ren cprcr r6, cpcr30 168165f2d28SLiu Yibin lsri r6, 29 169165f2d28SLiu Yibin lsli r6, 29 170205353faSGuo Ren addi r6, 0xe 171205353faSGuo Ren cpwcr r6, cpcr30 172f62e3162SGuo Ren 173aefd9461SGuo Ren movi r6, 0 174205353faSGuo Ren cpwcr r6, cpcr31 175081860b9SGuo Ren .endm 176081860b9SGuo Ren #endif /* __ASM_CSKY_ENTRY_H */ 177