| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | dmc_init_exynos4.c | 41 .control1 = CONTROL1_VAL,
54 writel((mem.control1 | (1 << mem.dll_resync)), in phy_control_reset()
56 writel((mem.control1 | (0 << mem.dll_resync)), in phy_control_reset()
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
105 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
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| H A D | exynos4_setup.h | 413 unsigned control1; member
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| /openbmc/openbmc/meta-ufispace/meta-ncplite/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-control | 27 gpioset --hold-period 50ms -t0 power-chassis-control1=1
38 gpioset --hold-period 50ms -t0 power-chassis-control1=0
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| /openbmc/linux/drivers/regulator/ |
| H A D | max8973-regulator.c | 322 uint8_t control1 = 0; in max8973_init_dcdc() local
332 control1 = data & MAX8973_RAMP_MASK; in max8973_init_dcdc()
333 switch (control1) { in max8973_init_dcdc()
349 control1 |= MAX8973_SNS_ENABLE; in max8973_init_dcdc()
352 control1 |= MAX8973_NFSR_ENABLE; in max8973_init_dcdc()
355 control1 |= MAX8973_AD_ENABLE; in max8973_init_dcdc()
358 control1 |= MAX8973_BIAS_ENABLE; in max8973_init_dcdc()
365 control1 |= MAX8973_FREQSHIFT_9PER; in max8973_init_dcdc()
412 ret = regmap_write(max->regmap, MAX8973_CONTROL1, control1); in max8973_init_dcdc()
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| /openbmc/linux/drivers/dma/dw-edma/ |
| H A D | dw-hdma-v0-regs.h | 56 u32 control1; /* 0x0034 */ member
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| H A D | dw-hdma-v0-debugfs.c | 96 CTX_REGISTER(dw, control1, dir, ch), in dw_hdma_debugfs_regs_ch()
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| H A D | dw-hdma-v0-core.c | 248 SET_CH_32(dw, chan->dir, chan->id, control1, HDMA_V0_LINKLIST_EN); in dw_hdma_v0_core_start()
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| /openbmc/linux/drivers/crypto/ |
| H A D | mxs-dcp.c | 50 uint32_t control1; member
266 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128; in mxs_dcp_run_aes()
269 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB; in mxs_dcp_run_aes()
271 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; in mxs_dcp_run_aes()
570 desc->control1 = actx->alg; in mxs_dcp_run_sha()
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| /openbmc/linux/drivers/media/platform/mediatek/mdp3/ |
| H A D | mdp_sm_mt8183.h | 73 u32 control1; member
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| H A D | mtk-mdp3-comp.c | 308 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); in config_rsz_frame()
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| /openbmc/linux/include/linux/amba/ |
| H A D | pl080.h | 214 u32 control1; member
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| /openbmc/linux/drivers/net/wireless/broadcom/b43/ |
| H A D | dma.h | 145 __le32 control1; member
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| H A D | dma.c | 208 desc->dma64.control1 = cpu_to_le32(ctl1); in op64_fill_descriptor()
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| /openbmc/linux/drivers/crypto/inside-secure/ |
| H A D | safexcel.h | 378 __le32 control1; member
597 u32 control1; member
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| H A D | safexcel_hash.c | 116 cdesc->control_data.control1 = 0; in safexcel_context_control()
196 cdesc->control_data.control1 |= in safexcel_context_control()
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| H A D | safexcel_cipher.c | 513 cdesc->control_data.control1 = ctx->mode; in safexcel_context_control()
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| /openbmc/linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-ufispace-ncplite.dts | 351 /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","",
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| /openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_link.c | 5270 u16 control1; in bnx2x_initialize_sgmii_process() local
5277 &control1); in bnx2x_initialize_sgmii_process()
5278 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; in bnx2x_initialize_sgmii_process()
5280 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | in bnx2x_initialize_sgmii_process()
5286 control1); in bnx2x_initialize_sgmii_process()
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| /openbmc/linux/drivers/net/wireless/marvell/ |
| H A D | mwl8k.c | 4472 __le16 control1; member
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