Searched refs:cntval_mask (Results 1 – 9 of 9) sorted by relevance
535 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in zhaoxin_pmu_init()552 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in zhaoxin_pmu_init()
226 .cntval_mask = (1ULL << 32) - 1,
308 .cntval_mask = (1ULL << 40) - 1,
1026 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in p4_pmu_set_period()1359 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
1381 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
6019 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()6897 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
1280 .cntval_mask = (1ULL << 48) - 1,
767 u64 cntval_mask; member
1412 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()2049 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in x86_pmu_show_pmu_cap()