Searched refs:cmd_sts (Results 1 – 5 of 5) sorted by relevance
407 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; in armdfec_init_rx_desc_ring()552 u32 cmd_sts, temp; in armdfec_send() local565 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; in armdfec_send()566 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; in armdfec_send()567 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; in armdfec_send()568 p_txdesc->cmd_sts |= TX_EN_INT; in armdfec_send()580 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()581 while (cmd_sts & BUF_OWNED_BY_DMA) { in armdfec_send()583 if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == in armdfec_send()588 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()[all …]
411 p_rx_desc->cmd_sts = in mvgbe_init_rx_desc_ring()578 u32 cmd_sts; in __mvgbe_send() local593 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; in __mvgbe_send()594 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; in __mvgbe_send()595 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; in __mvgbe_send()596 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; in __mvgbe_send()613 cmd_sts = readl(&p_txdesc->cmd_sts); in __mvgbe_send()614 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { in __mvgbe_send()616 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == in __mvgbe_send()618 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { in __mvgbe_send()[all …]
135 u32 cmd_sts; /* Command/status field */ member143 u32 cmd_sts; /* Descriptor command status */ member
467 u32 cmd_sts; /* Descriptor command status */ member475 u32 cmd_sts; /* Descriptor command status */ member
23 u32 cmd_sts; member131 writel(cmd, &priv->regs->cmd_sts); in ast2600_i2c_read_data()160 writel(cmd, &priv->regs->cmd_sts); in ast2600_i2c_write_data()183 writel(cmd, &priv->regs->cmd_sts); in ast2600_i2c_write_data()202 u32 csr = readl(&priv->regs->cmd_sts); in ast2600_i2c_deblock()213 csr = readl(&priv->regs->cmd_sts); in ast2600_i2c_deblock()218 writel(AST2600_I2CM_RECOVER_CMD_EN, &priv->regs->cmd_sts); in ast2600_i2c_deblock()