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Searched refs:cmd_hdr (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/hw/display/
H A Dvirtio-gpu-virgl.c880 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr); in virtio_gpu_virgl_process_cmd()
883 switch (cmd->cmd_hdr.type) { in virtio_gpu_virgl_process_cmd()
967 cmd->cmd_hdr.type, cmd->error); in virtio_gpu_virgl_process_cmd()
971 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { in virtio_gpu_virgl_process_cmd()
976 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); in virtio_gpu_virgl_process_cmd()
978 if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX) { in virtio_gpu_virgl_process_cmd()
979 virgl_renderer_context_create_fence(cmd->cmd_hdr.ctx_id, in virtio_gpu_virgl_process_cmd()
981 cmd->cmd_hdr.ring_idx, in virtio_gpu_virgl_process_cmd()
982 cmd->cmd_hdr in virtio_gpu_virgl_process_cmd()
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H A Dvirtio-gpu-rutabaga.c760 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr); in virtio_gpu_rutabaga_process_cmd()
762 switch (cmd->cmd_hdr.type) { in virtio_gpu_rutabaga_process_cmd()
839 cmd->cmd_hdr.type, cmd->error); in virtio_gpu_rutabaga_process_cmd()
843 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { in virtio_gpu_rutabaga_process_cmd()
848 fence.flags = cmd->cmd_hdr.flags; in virtio_gpu_rutabaga_process_cmd()
849 fence.ctx_id = cmd->cmd_hdr.ctx_id; in virtio_gpu_rutabaga_process_cmd()
850 fence.fence_id = cmd->cmd_hdr.fence_id; in virtio_gpu_rutabaga_process_cmd()
851 fence.ring_idx = cmd->cmd_hdr.ring_idx; in virtio_gpu_rutabaga_process_cmd()
853 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); in virtio_gpu_rutabaga_process_cmd()
874 uint32_t target_ctx_specific = cmd->cmd_hdr.flags & in virtio_gpu_rutabaga_aio_cb()
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H A Dvirtio-gpu.c167 if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE) { in virtio_gpu_ctrl_response()
169 resp->fence_id = cmd->cmd_hdr.fence_id; in virtio_gpu_ctrl_response()
170 resp->ctx_id = cmd->cmd_hdr.ctx_id; in virtio_gpu_ctrl_response()
964 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr); in virtio_gpu_simple_process_cmd()
965 virtio_gpu_ctrl_hdr_bswap(&cmd->cmd_hdr); in virtio_gpu_simple_process_cmd()
967 switch (cmd->cmd_hdr.type) { in virtio_gpu_simple_process_cmd()
1053 if (!cmd->finished && !(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { in virtio_gpu_process_cmdq()
1054 trace_virtio_gpu_cmd_suspended(cmd->cmd_hdr.type); in virtio_gpu_process_cmdq()
1084 trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id); in virtio_gpu_process_fenceq()
/openbmc/qemu/contrib/vhost-user-gpu/
H A Dvirgl.c486 switch (cmd->cmd_hdr.type) { in vg_virgl_process_cmd()
547 g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type); in vg_virgl_process_cmd()
558 cmd->cmd_hdr.type, cmd->error); in vg_virgl_process_cmd()
563 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { in vg_virgl_process_cmd()
569 cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); in vg_virgl_process_cmd()
570 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); in vg_virgl_process_cmd()
584 if (cmd->cmd_hdr.fence_id > fence) { in virgl_write_fence()
587 g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id); in virgl_write_fence()
H A Dvhost-user-gpu.c238 if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE) { in vg_ctrl_response()
240 resp->fence_id = cmd->cmd_hdr.fence_id; in vg_ctrl_response()
241 resp->ctx_id = cmd->cmd_hdr.ctx_id; in vg_ctrl_response()
275 assert(cmd->cmd_hdr.type == VIRTIO_GPU_CMD_GET_DISPLAY_INFO); in get_display_info_cb()
314 assert(cmd->cmd_hdr.type == VIRTIO_GPU_CMD_GET_EDID); in get_edid_cb()
862 switch (cmd->cmd_hdr.type) { in vg_process_cmd()
891 g_warning("TODO handle ctrl %x\n", cmd->cmd_hdr.type); in vg_process_cmd()
923 0, &cmd->cmd_hdr, sizeof(cmd->cmd_hdr)); in vg_handle_ctrl()
924 if (len != sizeof(cmd->cmd_hdr)) { in vg_handle_ctrl()
926 __func__, len, sizeof(cmd->cmd_hdr)); in vg_handle_ctrl()
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H A Dvugpu.h160 struct virtio_gpu_ctrl_hdr cmd_hdr; member
/openbmc/u-boot/drivers/ata/
H A Dfsl_sata.c80 cmd_hdr_tbl_t *cmd_hdr; in init_sata() local
131 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align) in init_sata()
133 sata->cmd_hdr = cmd_hdr; in init_sata()
155 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda); in init_sata()
168 out_le32(&reg->chba, (u32)cmd_hdr & ~0x3); in init_sata()
296 cmd_hdr_entry_t *cmd_hdr; in fsl_ata_exec_ata_cmd() local
378 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag]; in fsl_ata_exec_ata_cmd()
380 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3); in fsl_ata_exec_ata_cmd()
384 cmd_hdr->prde_fis_len = cpu_to_le32(val32); in fsl_ata_exec_ata_cmd()
386 cmd_hdr->ttl = cpu_to_le32(ttl); in fsl_ata_exec_ata_cmd()
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H A Dfsl_sata.h301 cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */ member
H A Ddwc_ahsata.c353 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + in ahci_fill_cmd_slot() local
356 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); in ahci_fill_cmd_slot()
357 cmd_hdr->opts = cpu_to_le32(opts); in ahci_fill_cmd_slot()
358 cmd_hdr->status = 0; in ahci_fill_cmd_slot()
/openbmc/qemu/include/hw/virtio/
H A Dvirtio-gpu.h138 struct virtio_gpu_ctrl_hdr cmd_hdr; member