Home
last modified time | relevance | path

Searched refs:cmask (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c37 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) in riscv_pmu_generate_fdt_node() argument
55 fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); in riscv_pmu_generate_fdt_node()
60 fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); in riscv_pmu_generate_fdt_node()
65 fdt_event_ctr_map[8] = cpu_to_be32(cmask); in riscv_pmu_generate_fdt_node()
70 fdt_event_ctr_map[11] = cpu_to_be32(cmask); in riscv_pmu_generate_fdt_node()
75 fdt_event_ctr_map[14] = cpu_to_be32(cmask); in riscv_pmu_generate_fdt_node()
H A Dpmu.h34 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
/openbmc/qemu/hw/pci/
H A Dslotid_cap.c35 d->cmask[cap + PCI_SID_ESR] = 0xff; in slotid_cap_init()
H A Dpci.c802 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { in get_pci_config_device()
806 s->cmask[i], s->wmask[i], s->w1cmask[i]); in get_pci_config_device()
1016 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); in pci_init_cmask()
1017 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); in pci_init_cmask()
1018 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; in pci_init_cmask()
1019 dev->cmask[PCI_REVISION_ID] = 0xff; in pci_init_cmask()
1020 dev->cmask[PCI_CLASS_PROG] = 0xff; in pci_init_cmask()
1021 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); in pci_init_cmask()
1022 dev->cmask[PCI_HEADER_TYPE] = 0xff; in pci_init_cmask()
1023 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; in pci_init_cmask()
[all …]
H A Dpcie.c74 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; in pcie_cap_v1_fill() local
111 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); in pcie_cap_v1_fill()
729 pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
1085 memset(dev->cmask + offset, 0xFF, size); in pcie_add_capability()
H A Dpcie_sriov.c241 pci_set_quad(dev->cmask + addr, ~0ULL); in pcie_sriov_pf_init_vf_bar()
244 pci_set_long(dev->cmask + addr, 0xffffffff); in pcie_sriov_pf_init_vf_bar()
H A Dshpc.c669 shpc->cmask = g_malloc0(SHPC_SIZEOF(d)); in shpc_init()
740 g_free(shpc->cmask); in shpc_free()
H A Dpcie_aer.c755 pci_set_long(dev->cmask + pos + PCI_ERR_ROOT_STATUS, in pcie_aer_root_init()
/openbmc/qemu/include/hw/pci/
H A Dshpc.h21 uint8_t *cmask; member
H A Dpci_device.h71 uint8_t *cmask; member
/openbmc/qemu/hw/vfio/
H A Dcpr.c107 pdev->cmask[i] &= vdev->emulated_config_bits[i]; in vfio_cpr_pci_pre_load()
H A Dpci.c2328 memset(pdev->cmask + pos + 3, 0, size - 3); in vfio_add_vendor_specific_cap()
/openbmc/qemu/target/sparc/
H A Dinsns.decode92 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
H A Dtranslate.c2870 if (a->cmask) { in trans_MEMBAR()
/openbmc/qemu/fpu/
H A Dsoftfloat.c467 static inline bool cmask_is_only_normals(int cmask) in cmask_is_only_normals() argument
469 return !(cmask & ~float_cmask_anynorm); in cmask_is_only_normals()