Searched refs:clk_ctl (Results 1 – 3 of 3) sorted by relevance
895 int clk_ctl = 0; in sgtl5000_set_clock() local920 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()923 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()935 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()938 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()941 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()944 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()959 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << in sgtl5000_set_clock()963 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << in sgtl5000_set_clock()967 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << in sgtl5000_set_clock()[all …]
478 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate); in cs35l35_hw_params() local480 if (clk_ctl < 0) { in cs35l35_hw_params()487 CS35L35_CLK_CTL2_MASK, clk_ctl); in cs35l35_hw_params()499 errata_chk = (clk_ctl & CS35L35_SP_RATE_MASK) >> CS35L35_SP_RATE_SHIFT; in cs35l35_hw_params()
232 int clk_ctl; member863 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()1007 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()1381 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()1863 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()1867 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()