Lines Matching refs:clk_ctl
895 int clk_ctl = 0; in sgtl5000_set_clock() local
920 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
923 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
926 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()
935 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
938 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
941 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
944 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()
959 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << in sgtl5000_set_clock()
963 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << in sgtl5000_set_clock()
967 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << in sgtl5000_set_clock()
973 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << in sgtl5000_set_clock()
986 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { in sgtl5000_set_clock()
1029 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); in sgtl5000_set_clock()
1032 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); in sgtl5000_set_clock()