Searched refs:clk_csr (Results 1 – 14 of 14) sorted by relevance
100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()183 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()289 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c22()329 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c45()389 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c22()430 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c45()
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()77 plat->clk_csr = 5; in snps_gmac5_default_data()
448 plat->clk_csr = -1; in stmmac_probe_config_dt()449 if (of_property_read_u32(np, "snps,clk-csr", &plat->clk_csr)) in stmmac_probe_config_dt()450 of_property_read_u32(np, "clk_csr", &plat->clk_csr); in stmmac_probe_config_dt()
14 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
331 priv->clk_csr = 0x03; in stmmac_clk_csr_set()333 priv->clk_csr = 0x02; in stmmac_clk_csr_set()335 priv->clk_csr = 0x01; in stmmac_clk_csr_set()337 priv->clk_csr = 0; in stmmac_clk_csr_set()342 priv->clk_csr = 0x5; in stmmac_clk_csr_set()344 priv->clk_csr = 0x4; in stmmac_clk_csr_set()346 priv->clk_csr = 0x3; in stmmac_clk_csr_set()348 priv->clk_csr = 0x2; in stmmac_clk_csr_set()350 priv->clk_csr = 0x1; in stmmac_clk_csr_set()352 priv->clk_csr = 0x0; in stmmac_clk_csr_set()[all …]
261 int clk_csr; member
419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()456 plat->clk_csr = 5; in intel_mgbe_common_data()
46 int clk_csr; member
250 int clk_csr; member
176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()2163 if (!priv->plat->clk_csr) in sxgbe_drv_probe()2166 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
489 int clk_csr; member
475 unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; in qat_hal_clr_reset() local494 csr_val = GET_CAP_CSR(handle, clk_csr); in qat_hal_clr_reset()496 SET_CAP_CSR(handle, clk_csr, csr_val); in qat_hal_clr_reset()
370 int clk_csr;