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Searched refs:chipset (Results 1 – 21 of 21) sorted by relevance

/openbmc/u-boot/board/emulation/
H A DKconfig17 chipset platform and '-M q35', a Q35/ICH9 chipset platform.
/openbmc/u-boot/board/dfi/dfi-bt700/acpi/
H A Dmainboard.asl12 /* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */
/openbmc/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/
H A Dmainboard.asl12 /* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
/openbmc/openpower-proc-control/
H A DREADME.md3 Contains procedures that interact with the OpenPower nest chipset.
/openbmc/u-boot/drivers/net/
H A Drtl8169.c324 int chipset; member
409 tpc->chipset = i; in rtl8169_init_board()
418 tpc->chipset = 0; in rtl8169_init_board()
706 rtl_chip_info[tpc->chipset].RxConfigMask); in rtl8169_set_rx_mode()
742 if (tpc->chipset <= 5) in rtl8169_hw_start()
752 rtl_chip_info[tpc->chipset].RxConfigMask); in rtl8169_hw_start()
780 if (tpc->chipset > 5) in rtl8169_hw_start()
976 printf("chipset = %d\n", tpc->chipset); in rtl_init()
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/
H A Dpython3-luma-oled_3.14.0.bb4 SSD1325, SSD1327, SSD1331, SSD1351 or SH1106 chipset"
/openbmc/qemu/docs/system/
H A Dtarget-mips.rst67 - VT82C686 chipset as South Bridge
69 - RTL8139D as a network card chipset
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel,irq-router.txt18 be specified. The 8-bit ACTL register is seen on ICH series chipset, like
19 ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/ssiapi/
H A Dssiapi_1.3.0.bb4 … manage storage devices including creating and managing Raid arrays on systems with Intel chipset."
/openbmc/u-boot/doc/driver-model/
H A Dpci-info.txt97 to a downstream device Topcliff chipset. Inside Topcliff chipset, it has a
98 PCIe-to-PCI bridge and all the chipset integrated devices like the PCI UART
/openbmc/openbmc/meta-openpower/recipes-phosphor/host/
H A Dop-proc-control_git.bb2 DESCRIPTION = "Provides procedures that run against the host chipset"
/openbmc/u-boot/board/intel/
H A DKconfig33 and Panther Point chipset. The board has 4GB RAM, with some other
/openbmc/u-boot/arch/x86/dts/
H A Dcrownbay.dts186 * chipset is connected to TunnelCreek
/openbmc/docs/designs/
H A Dhw-fault-monitor.md17 purposes. The information logged would include a wide variety of chipset
99 capability). The crash dump includes chipset registers but doesn’t include
/openbmc/u-boot/arch/x86/
H A DKconfig96 chipset which consume less power than most of the x86
347 to set up SDRAM and other chipset specific initialization.
735 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
751 Intel ICH6 compatible chipset pinctrl driver. It needs to work
/openbmc/u-boot/arch/x86/include/asm/acpi/
H A Dirqlinks.asl10 * Intel chipset PIRQ routing control ASL description
/openbmc/u-boot/doc/
H A DREADME.x86195 memory controller, chipset and certain bus interfaces.
429 This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
430 also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
988 the chipset datasheet which lists all the available PCI devices. For example on
991 The reliable source is the hardware as sometimes chipset datasheet is not 100%
1006 chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
/openbmc/qemu/docs/system/devices/
H A Dusb.rst47 the PIIX3 chipset. The USB 1.1 bus will carry the name ``usb-bus.0``.
/openbmc/intel-ipmi-oem/src/
H A Doemcommands.cpp89 chipset = 7, enumerator
3202 bmcSource = static_cast<uint8_t>(NmiSource::chipset); in ipmiOEMGetNmiSource()
3251 case NmiSource::chipset: in ipmiOEMSetNmiSource()
/openbmc/openbmc/poky/documentation/kernel-dev/
H A Dcommon.rst649 the Broadcom 2708/2709 chipset::
/openbmc/u-boot/
H A DREADME3058 defines the spacing between FDC chipset registers
3065 the FDC chipset. (default value 0)