19f806850SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
24630b130SAaron Sierra /*
34630b130SAaron Sierra * lpc_ich.c - LPC interface for Intel ICH
44630b130SAaron Sierra *
54630b130SAaron Sierra * LPC bridge function of the Intel ICH contains many other
64630b130SAaron Sierra * functional units, such as Interrupt controllers, Timers,
74630b130SAaron Sierra * Power Management, System Management, GPIO, RTC, and LPC
84630b130SAaron Sierra * Configuration Registers.
94630b130SAaron Sierra *
104630b130SAaron Sierra * This driver is derived from lpc_sch.
117064d7d8STan Jui Nee *
127064d7d8STan Jui Nee * Copyright (c) 2017, 2021-2022 Intel Corporation
134630b130SAaron Sierra * Copyright (c) 2011 Extreme Engineering Solution, Inc.
144630b130SAaron Sierra * Author: Aaron Sierra <asierra@xes-inc.com>
154630b130SAaron Sierra *
164630b130SAaron Sierra * This driver supports the following I/O Controller hubs:
174630b130SAaron Sierra * (See the intel documentation on http://developer.intel.com.)
184630b130SAaron Sierra * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
194630b130SAaron Sierra * document number 290687-002, 298242-027: 82801BA (ICH2)
204630b130SAaron Sierra * document number 290733-003, 290739-013: 82801CA (ICH3-S)
214630b130SAaron Sierra * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
224630b130SAaron Sierra * document number 290744-001, 290745-025: 82801DB (ICH4)
234630b130SAaron Sierra * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
244630b130SAaron Sierra * document number 273599-001, 273645-002: 82801E (C-ICH)
254630b130SAaron Sierra * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
264630b130SAaron Sierra * document number 300641-004, 300884-013: 6300ESB
274630b130SAaron Sierra * document number 301473-002, 301474-026: 82801F (ICH6)
284630b130SAaron Sierra * document number 313082-001, 313075-006: 631xESB, 632xESB
294630b130SAaron Sierra * document number 307013-003, 307014-024: 82801G (ICH7)
304630b130SAaron Sierra * document number 322896-001, 322897-001: NM10
314630b130SAaron Sierra * document number 313056-003, 313057-017: 82801H (ICH8)
324630b130SAaron Sierra * document number 316972-004, 316973-012: 82801I (ICH9)
334630b130SAaron Sierra * document number 319973-002, 319974-002: 82801J (ICH10)
344630b130SAaron Sierra * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
354630b130SAaron Sierra * document number 320066-003, 320257-008: EP80597 (IICH)
364630b130SAaron Sierra * document number 324645-001, 324646-001: Cougar Point (CPT)
374630b130SAaron Sierra */
384630b130SAaron Sierra
394630b130SAaron Sierra #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
404630b130SAaron Sierra
414630b130SAaron Sierra #include <linux/kernel.h>
424630b130SAaron Sierra #include <linux/module.h>
434630b130SAaron Sierra #include <linux/errno.h>
444630b130SAaron Sierra #include <linux/acpi.h>
454630b130SAaron Sierra #include <linux/pci.h>
467064d7d8STan Jui Nee #include <linux/pinctrl/pinctrl.h>
474630b130SAaron Sierra #include <linux/mfd/core.h>
484630b130SAaron Sierra #include <linux/mfd/lpc_ich.h>
49420b54deSMatt Fleming #include <linux/platform_data/itco_wdt.h>
5055979319SAndy Shevchenko #include <linux/platform_data/x86/p2sb.h>
514630b130SAaron Sierra
524630b130SAaron Sierra #define ACPIBASE 0x40
534630b130SAaron Sierra #define ACPIBASE_GPE_OFF 0x28
544630b130SAaron Sierra #define ACPIBASE_GPE_END 0x2f
55887c8ec7SAaron Sierra #define ACPIBASE_SMI_OFF 0x30
56887c8ec7SAaron Sierra #define ACPIBASE_SMI_END 0x33
57eb71d4deSPeter Tyser #define ACPIBASE_PMC_OFF 0x08
58eb71d4deSPeter Tyser #define ACPIBASE_PMC_END 0x0c
59887c8ec7SAaron Sierra #define ACPIBASE_TCO_OFF 0x60
60887c8ec7SAaron Sierra #define ACPIBASE_TCO_END 0x7f
61eb71d4deSPeter Tyser #define ACPICTRL_PMCBASE 0x44
624630b130SAaron Sierra
63887c8ec7SAaron Sierra #define ACPIBASE_GCS_OFF 0x3410
64887c8ec7SAaron Sierra #define ACPIBASE_GCS_END 0x3414
65887c8ec7SAaron Sierra
66ff00d7a3SMika Westerberg #define SPIBASE_BYT 0x54
67ff00d7a3SMika Westerberg #define SPIBASE_BYT_SZ 512
68ff00d7a3SMika Westerberg #define SPIBASE_BYT_EN BIT(1)
69cd149effSMika Westerberg #define BYT_BCR 0xfc
70cd149effSMika Westerberg #define BYT_BCR_WPD BIT(0)
71ff00d7a3SMika Westerberg
72ff00d7a3SMika Westerberg #define SPIBASE_LPT 0x3800
73ff00d7a3SMika Westerberg #define SPIBASE_LPT_SZ 512
74ff00d7a3SMika Westerberg #define BCR 0xdc
75ff00d7a3SMika Westerberg #define BCR_WPD BIT(0)
76ff00d7a3SMika Westerberg
7701560f6bSAaron Sierra #define GPIOBASE_ICH0 0x58
7801560f6bSAaron Sierra #define GPIOCTRL_ICH0 0x5C
7901560f6bSAaron Sierra #define GPIOBASE_ICH6 0x48
8001560f6bSAaron Sierra #define GPIOCTRL_ICH6 0x4C
814630b130SAaron Sierra
82887c8ec7SAaron Sierra #define RCBABASE 0xf0
83887c8ec7SAaron Sierra
84887c8ec7SAaron Sierra #define wdt_io_res(i) wdt_res(0, i)
85887c8ec7SAaron Sierra #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
86887c8ec7SAaron Sierra #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
87887c8ec7SAaron Sierra
8801560f6bSAaron Sierra struct lpc_ich_priv {
8901560f6bSAaron Sierra int chipset;
90429b941aSPeter Tyser
91429b941aSPeter Tyser int abase; /* ACPI base */
92eb71d4deSPeter Tyser int actrl_pbase; /* ACPI control or PMC base */
93429b941aSPeter Tyser int gbase; /* GPIO base */
94429b941aSPeter Tyser int gctrl; /* GPIO control */
95429b941aSPeter Tyser
96eb71d4deSPeter Tyser int abase_save; /* Cached ACPI base value */
97eb71d4deSPeter Tyser int actrl_pbase_save; /* Cached ACPI control or PMC base value */
98429b941aSPeter Tyser int gctrl_save; /* Cached GPIO control value */
9901560f6bSAaron Sierra };
1004630b130SAaron Sierra
101887c8ec7SAaron Sierra static struct resource wdt_ich_res[] = {
102887c8ec7SAaron Sierra /* ACPI - TCO */
103887c8ec7SAaron Sierra {
104887c8ec7SAaron Sierra .flags = IORESOURCE_IO,
105887c8ec7SAaron Sierra },
106887c8ec7SAaron Sierra /* ACPI - SMI */
107887c8ec7SAaron Sierra {
108887c8ec7SAaron Sierra .flags = IORESOURCE_IO,
109887c8ec7SAaron Sierra },
110eb71d4deSPeter Tyser /* GCS or PMC */
111887c8ec7SAaron Sierra {
112887c8ec7SAaron Sierra .flags = IORESOURCE_MEM,
113887c8ec7SAaron Sierra },
114887c8ec7SAaron Sierra };
115887c8ec7SAaron Sierra
1164630b130SAaron Sierra static struct resource gpio_ich_res[] = {
1174630b130SAaron Sierra /* GPIO */
1184630b130SAaron Sierra {
1194630b130SAaron Sierra .flags = IORESOURCE_IO,
1204630b130SAaron Sierra },
1214630b130SAaron Sierra /* ACPI - GPE0 */
1224630b130SAaron Sierra {
1234630b130SAaron Sierra .flags = IORESOURCE_IO,
1244630b130SAaron Sierra },
1254630b130SAaron Sierra };
1264630b130SAaron Sierra
127ff00d7a3SMika Westerberg static struct resource intel_spi_res[] = {
128ff00d7a3SMika Westerberg {
129ff00d7a3SMika Westerberg .flags = IORESOURCE_MEM,
130ff00d7a3SMika Westerberg }
131ff00d7a3SMika Westerberg };
132ff00d7a3SMika Westerberg
1333dab794fSAaron Sierra static struct mfd_cell lpc_ich_wdt_cell = {
134887c8ec7SAaron Sierra .name = "iTCO_wdt",
135887c8ec7SAaron Sierra .num_resources = ARRAY_SIZE(wdt_ich_res),
136887c8ec7SAaron Sierra .resources = wdt_ich_res,
137887c8ec7SAaron Sierra .ignore_resource_conflicts = true,
1383dab794fSAaron Sierra };
1393dab794fSAaron Sierra
1403dab794fSAaron Sierra static struct mfd_cell lpc_ich_gpio_cell = {
1414630b130SAaron Sierra .name = "gpio_ich",
1424630b130SAaron Sierra .num_resources = ARRAY_SIZE(gpio_ich_res),
1434630b130SAaron Sierra .resources = gpio_ich_res,
1444630b130SAaron Sierra .ignore_resource_conflicts = true,
1454630b130SAaron Sierra };
1464630b130SAaron Sierra
1477064d7d8STan Jui Nee #define APL_GPIO_NORTH 0
1487064d7d8STan Jui Nee #define APL_GPIO_NORTHWEST 1
1497064d7d8STan Jui Nee #define APL_GPIO_WEST 2
1507064d7d8STan Jui Nee #define APL_GPIO_SOUTHWEST 3
1517064d7d8STan Jui Nee #define APL_GPIO_NR_DEVICES 4
1527064d7d8STan Jui Nee
1537064d7d8STan Jui Nee /* Offset data for Apollo Lake GPIO controllers */
1547064d7d8STan Jui Nee static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = {
1557064d7d8STan Jui Nee [APL_GPIO_NORTH] = 0xc50000,
1567064d7d8STan Jui Nee [APL_GPIO_NORTHWEST] = 0xc40000,
1577064d7d8STan Jui Nee [APL_GPIO_WEST] = 0xc70000,
1587064d7d8STan Jui Nee [APL_GPIO_SOUTHWEST] = 0xc00000,
1597064d7d8STan Jui Nee };
1607064d7d8STan Jui Nee
1617064d7d8STan Jui Nee #define APL_GPIO_RESOURCE_SIZE 0x1000
1627064d7d8STan Jui Nee
1637064d7d8STan Jui Nee #define APL_GPIO_IRQ 14
1647064d7d8STan Jui Nee
1657064d7d8STan Jui Nee static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
1667064d7d8STan Jui Nee [APL_GPIO_NORTH] = {
1677064d7d8STan Jui Nee DEFINE_RES_MEM(0, 0),
1687064d7d8STan Jui Nee DEFINE_RES_IRQ(APL_GPIO_IRQ),
1697064d7d8STan Jui Nee },
1707064d7d8STan Jui Nee [APL_GPIO_NORTHWEST] = {
1717064d7d8STan Jui Nee DEFINE_RES_MEM(0, 0),
1727064d7d8STan Jui Nee DEFINE_RES_IRQ(APL_GPIO_IRQ),
1737064d7d8STan Jui Nee },
1747064d7d8STan Jui Nee [APL_GPIO_WEST] = {
1757064d7d8STan Jui Nee DEFINE_RES_MEM(0, 0),
1767064d7d8STan Jui Nee DEFINE_RES_IRQ(APL_GPIO_IRQ),
1777064d7d8STan Jui Nee },
1787064d7d8STan Jui Nee [APL_GPIO_SOUTHWEST] = {
1797064d7d8STan Jui Nee DEFINE_RES_MEM(0, 0),
1807064d7d8STan Jui Nee DEFINE_RES_IRQ(APL_GPIO_IRQ),
1817064d7d8STan Jui Nee },
1827064d7d8STan Jui Nee };
1837064d7d8STan Jui Nee
1847064d7d8STan Jui Nee static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
1857064d7d8STan Jui Nee [APL_GPIO_NORTH] = {
1867064d7d8STan Jui Nee .name = "apollolake-pinctrl",
1877064d7d8STan Jui Nee .id = APL_GPIO_NORTH,
1887064d7d8STan Jui Nee .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
1897064d7d8STan Jui Nee .resources = apl_gpio_resources[APL_GPIO_NORTH],
1907064d7d8STan Jui Nee .ignore_resource_conflicts = true,
1917064d7d8STan Jui Nee },
1927064d7d8STan Jui Nee [APL_GPIO_NORTHWEST] = {
1937064d7d8STan Jui Nee .name = "apollolake-pinctrl",
1947064d7d8STan Jui Nee .id = APL_GPIO_NORTHWEST,
1957064d7d8STan Jui Nee .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
1967064d7d8STan Jui Nee .resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
1977064d7d8STan Jui Nee .ignore_resource_conflicts = true,
1987064d7d8STan Jui Nee },
1997064d7d8STan Jui Nee [APL_GPIO_WEST] = {
2007064d7d8STan Jui Nee .name = "apollolake-pinctrl",
2017064d7d8STan Jui Nee .id = APL_GPIO_WEST,
2027064d7d8STan Jui Nee .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
2037064d7d8STan Jui Nee .resources = apl_gpio_resources[APL_GPIO_WEST],
2047064d7d8STan Jui Nee .ignore_resource_conflicts = true,
2057064d7d8STan Jui Nee },
2067064d7d8STan Jui Nee [APL_GPIO_SOUTHWEST] = {
2077064d7d8STan Jui Nee .name = "apollolake-pinctrl",
2087064d7d8STan Jui Nee .id = APL_GPIO_SOUTHWEST,
2097064d7d8STan Jui Nee .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
2107064d7d8STan Jui Nee .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
2117064d7d8STan Jui Nee .ignore_resource_conflicts = true,
2127064d7d8STan Jui Nee },
2137064d7d8STan Jui Nee };
214ff00d7a3SMika Westerberg
215ff00d7a3SMika Westerberg static struct mfd_cell lpc_ich_spi_cell = {
216ff00d7a3SMika Westerberg .name = "intel-spi",
217ff00d7a3SMika Westerberg .num_resources = ARRAY_SIZE(intel_spi_res),
218ff00d7a3SMika Westerberg .resources = intel_spi_res,
219ff00d7a3SMika Westerberg .ignore_resource_conflicts = true,
220ff00d7a3SMika Westerberg };
221ff00d7a3SMika Westerberg
2224630b130SAaron Sierra /* chipset related info */
2234630b130SAaron Sierra enum lpc_chipsets {
2244630b130SAaron Sierra LPC_ICH = 0, /* ICH */
2254630b130SAaron Sierra LPC_ICH0, /* ICH0 */
2264630b130SAaron Sierra LPC_ICH2, /* ICH2 */
2274630b130SAaron Sierra LPC_ICH2M, /* ICH2-M */
2284630b130SAaron Sierra LPC_ICH3, /* ICH3-S */
2294630b130SAaron Sierra LPC_ICH3M, /* ICH3-M */
2304630b130SAaron Sierra LPC_ICH4, /* ICH4 */
2314630b130SAaron Sierra LPC_ICH4M, /* ICH4-M */
2324630b130SAaron Sierra LPC_CICH, /* C-ICH */
2334630b130SAaron Sierra LPC_ICH5, /* ICH5 & ICH5R */
2344630b130SAaron Sierra LPC_6300ESB, /* 6300ESB */
2354630b130SAaron Sierra LPC_ICH6, /* ICH6 & ICH6R */
2364630b130SAaron Sierra LPC_ICH6M, /* ICH6-M */
2374630b130SAaron Sierra LPC_ICH6W, /* ICH6W & ICH6RW */
2384630b130SAaron Sierra LPC_631XESB, /* 631xESB/632xESB */
2394630b130SAaron Sierra LPC_ICH7, /* ICH7 & ICH7R */
2404630b130SAaron Sierra LPC_ICH7DH, /* ICH7DH */
2414630b130SAaron Sierra LPC_ICH7M, /* ICH7-M & ICH7-U */
2424630b130SAaron Sierra LPC_ICH7MDH, /* ICH7-M DH */
2434630b130SAaron Sierra LPC_NM10, /* NM10 */
2444630b130SAaron Sierra LPC_ICH8, /* ICH8 & ICH8R */
2454630b130SAaron Sierra LPC_ICH8DH, /* ICH8DH */
2464630b130SAaron Sierra LPC_ICH8DO, /* ICH8DO */
2474630b130SAaron Sierra LPC_ICH8M, /* ICH8M */
2484630b130SAaron Sierra LPC_ICH8ME, /* ICH8M-E */
2494630b130SAaron Sierra LPC_ICH9, /* ICH9 */
2504630b130SAaron Sierra LPC_ICH9R, /* ICH9R */
2514630b130SAaron Sierra LPC_ICH9DH, /* ICH9DH */
2524630b130SAaron Sierra LPC_ICH9DO, /* ICH9DO */
2534630b130SAaron Sierra LPC_ICH9M, /* ICH9M */
2544630b130SAaron Sierra LPC_ICH9ME, /* ICH9M-E */
2554630b130SAaron Sierra LPC_ICH10, /* ICH10 */
2564630b130SAaron Sierra LPC_ICH10R, /* ICH10R */
2574630b130SAaron Sierra LPC_ICH10D, /* ICH10D */
2584630b130SAaron Sierra LPC_ICH10DO, /* ICH10DO */
2594630b130SAaron Sierra LPC_PCH, /* PCH Desktop Full Featured */
2604630b130SAaron Sierra LPC_PCHM, /* PCH Mobile Full Featured */
2614630b130SAaron Sierra LPC_P55, /* P55 */
2624630b130SAaron Sierra LPC_PM55, /* PM55 */
2634630b130SAaron Sierra LPC_H55, /* H55 */
2644630b130SAaron Sierra LPC_QM57, /* QM57 */
2654630b130SAaron Sierra LPC_H57, /* H57 */
2664630b130SAaron Sierra LPC_HM55, /* HM55 */
2674630b130SAaron Sierra LPC_Q57, /* Q57 */
2684630b130SAaron Sierra LPC_HM57, /* HM57 */
2694630b130SAaron Sierra LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
2704630b130SAaron Sierra LPC_QS57, /* QS57 */
2714630b130SAaron Sierra LPC_3400, /* 3400 */
2724630b130SAaron Sierra LPC_3420, /* 3420 */
2734630b130SAaron Sierra LPC_3450, /* 3450 */
2744630b130SAaron Sierra LPC_EP80579, /* EP80579 */
2754630b130SAaron Sierra LPC_CPT, /* Cougar Point */
2764630b130SAaron Sierra LPC_CPTD, /* Cougar Point Desktop */
2774630b130SAaron Sierra LPC_CPTM, /* Cougar Point Mobile */
2784630b130SAaron Sierra LPC_PBG, /* Patsburg */
2794630b130SAaron Sierra LPC_DH89XXCC, /* DH89xxCC */
2804630b130SAaron Sierra LPC_PPT, /* Panther Point */
2814630b130SAaron Sierra LPC_LPT, /* Lynx Point */
2827fb9c1a4SJames Ralston LPC_LPT_LP, /* Lynx Point-LP */
2836e6680e3SJames Ralston LPC_WBG, /* Wellsburg */
2848477128fSJames Ralston LPC_AVN, /* Avoton SoC */
2856111ec70SPeter Tyser LPC_BAYTRAIL, /* Bay Trail SoC */
286283aae8aSSeth Heasley LPC_COLETO, /* Coleto Creek */
2875e90169cSJames Ralston LPC_WPT_LP, /* Wildcat Point-LP */
288ff0c9da0SAlan Cox LPC_BRASWELL, /* Braswell SoC */
2896223a309SAlexandra Yates LPC_LEWISBURG, /* Lewisburg */
290fea31042SJames Ralston LPC_9S, /* 9 Series */
29187eb832aSMika Westerberg LPC_APL, /* Apollo Lake SoC */
292a6450cb0SMika Westerberg LPC_GLK, /* Gemini Lake SoC */
293f36c1f62SPriyalee Kushwaha LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
2944630b130SAaron Sierra };
2954630b130SAaron Sierra
296a1ca138fSJingoo Han static struct lpc_ich_info lpc_chipset_info[] = {
2974630b130SAaron Sierra [LPC_ICH] = {
2984630b130SAaron Sierra .name = "ICH",
299887c8ec7SAaron Sierra .iTCO_version = 1,
3004630b130SAaron Sierra },
3014630b130SAaron Sierra [LPC_ICH0] = {
3024630b130SAaron Sierra .name = "ICH0",
303887c8ec7SAaron Sierra .iTCO_version = 1,
3044630b130SAaron Sierra },
3054630b130SAaron Sierra [LPC_ICH2] = {
3064630b130SAaron Sierra .name = "ICH2",
307887c8ec7SAaron Sierra .iTCO_version = 1,
3084630b130SAaron Sierra },
3094630b130SAaron Sierra [LPC_ICH2M] = {
3104630b130SAaron Sierra .name = "ICH2-M",
311887c8ec7SAaron Sierra .iTCO_version = 1,
3124630b130SAaron Sierra },
3134630b130SAaron Sierra [LPC_ICH3] = {
3144630b130SAaron Sierra .name = "ICH3-S",
315887c8ec7SAaron Sierra .iTCO_version = 1,
3164630b130SAaron Sierra },
3174630b130SAaron Sierra [LPC_ICH3M] = {
3184630b130SAaron Sierra .name = "ICH3-M",
319887c8ec7SAaron Sierra .iTCO_version = 1,
3204630b130SAaron Sierra },
3214630b130SAaron Sierra [LPC_ICH4] = {
3224630b130SAaron Sierra .name = "ICH4",
323887c8ec7SAaron Sierra .iTCO_version = 1,
3244630b130SAaron Sierra },
3254630b130SAaron Sierra [LPC_ICH4M] = {
3264630b130SAaron Sierra .name = "ICH4-M",
327887c8ec7SAaron Sierra .iTCO_version = 1,
3284630b130SAaron Sierra },
3294630b130SAaron Sierra [LPC_CICH] = {
3304630b130SAaron Sierra .name = "C-ICH",
331887c8ec7SAaron Sierra .iTCO_version = 1,
3324630b130SAaron Sierra },
3334630b130SAaron Sierra [LPC_ICH5] = {
3344630b130SAaron Sierra .name = "ICH5 or ICH5R",
335887c8ec7SAaron Sierra .iTCO_version = 1,
3364630b130SAaron Sierra },
3374630b130SAaron Sierra [LPC_6300ESB] = {
3384630b130SAaron Sierra .name = "6300ESB",
339887c8ec7SAaron Sierra .iTCO_version = 1,
3404630b130SAaron Sierra },
3414630b130SAaron Sierra [LPC_ICH6] = {
3424630b130SAaron Sierra .name = "ICH6 or ICH6R",
343887c8ec7SAaron Sierra .iTCO_version = 2,
3444630b130SAaron Sierra .gpio_version = ICH_V6_GPIO,
3454630b130SAaron Sierra },
3464630b130SAaron Sierra [LPC_ICH6M] = {
3474630b130SAaron Sierra .name = "ICH6-M",
348887c8ec7SAaron Sierra .iTCO_version = 2,
3494630b130SAaron Sierra .gpio_version = ICH_V6_GPIO,
3504630b130SAaron Sierra },
3514630b130SAaron Sierra [LPC_ICH6W] = {
3524630b130SAaron Sierra .name = "ICH6W or ICH6RW",
353887c8ec7SAaron Sierra .iTCO_version = 2,
3544630b130SAaron Sierra .gpio_version = ICH_V6_GPIO,
3554630b130SAaron Sierra },
3564630b130SAaron Sierra [LPC_631XESB] = {
3574630b130SAaron Sierra .name = "631xESB/632xESB",
358887c8ec7SAaron Sierra .iTCO_version = 2,
3594630b130SAaron Sierra .gpio_version = ICH_V6_GPIO,
3604630b130SAaron Sierra },
3614630b130SAaron Sierra [LPC_ICH7] = {
3624630b130SAaron Sierra .name = "ICH7 or ICH7R",
363887c8ec7SAaron Sierra .iTCO_version = 2,
3644630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3654630b130SAaron Sierra },
3664630b130SAaron Sierra [LPC_ICH7DH] = {
3674630b130SAaron Sierra .name = "ICH7DH",
368887c8ec7SAaron Sierra .iTCO_version = 2,
3694630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3704630b130SAaron Sierra },
3714630b130SAaron Sierra [LPC_ICH7M] = {
3724630b130SAaron Sierra .name = "ICH7-M or ICH7-U",
373887c8ec7SAaron Sierra .iTCO_version = 2,
3744630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3754630b130SAaron Sierra },
3764630b130SAaron Sierra [LPC_ICH7MDH] = {
3774630b130SAaron Sierra .name = "ICH7-M DH",
378887c8ec7SAaron Sierra .iTCO_version = 2,
3794630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3804630b130SAaron Sierra },
3814630b130SAaron Sierra [LPC_NM10] = {
3824630b130SAaron Sierra .name = "NM10",
383887c8ec7SAaron Sierra .iTCO_version = 2,
384117bbfe2SPeter Tyser .gpio_version = ICH_V7_GPIO,
3854630b130SAaron Sierra },
3864630b130SAaron Sierra [LPC_ICH8] = {
3874630b130SAaron Sierra .name = "ICH8 or ICH8R",
388887c8ec7SAaron Sierra .iTCO_version = 2,
3894630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3904630b130SAaron Sierra },
3914630b130SAaron Sierra [LPC_ICH8DH] = {
3924630b130SAaron Sierra .name = "ICH8DH",
393887c8ec7SAaron Sierra .iTCO_version = 2,
3944630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
3954630b130SAaron Sierra },
3964630b130SAaron Sierra [LPC_ICH8DO] = {
3974630b130SAaron Sierra .name = "ICH8DO",
398887c8ec7SAaron Sierra .iTCO_version = 2,
3994630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
4004630b130SAaron Sierra },
4014630b130SAaron Sierra [LPC_ICH8M] = {
4024630b130SAaron Sierra .name = "ICH8M",
403887c8ec7SAaron Sierra .iTCO_version = 2,
4044630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
4054630b130SAaron Sierra },
4064630b130SAaron Sierra [LPC_ICH8ME] = {
4074630b130SAaron Sierra .name = "ICH8M-E",
408887c8ec7SAaron Sierra .iTCO_version = 2,
4094630b130SAaron Sierra .gpio_version = ICH_V7_GPIO,
4104630b130SAaron Sierra },
4114630b130SAaron Sierra [LPC_ICH9] = {
4124630b130SAaron Sierra .name = "ICH9",
413887c8ec7SAaron Sierra .iTCO_version = 2,
4144630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4154630b130SAaron Sierra },
4164630b130SAaron Sierra [LPC_ICH9R] = {
4174630b130SAaron Sierra .name = "ICH9R",
418887c8ec7SAaron Sierra .iTCO_version = 2,
4194630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4204630b130SAaron Sierra },
4214630b130SAaron Sierra [LPC_ICH9DH] = {
4224630b130SAaron Sierra .name = "ICH9DH",
423887c8ec7SAaron Sierra .iTCO_version = 2,
4244630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4254630b130SAaron Sierra },
4264630b130SAaron Sierra [LPC_ICH9DO] = {
4274630b130SAaron Sierra .name = "ICH9DO",
428887c8ec7SAaron Sierra .iTCO_version = 2,
4294630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4304630b130SAaron Sierra },
4314630b130SAaron Sierra [LPC_ICH9M] = {
4324630b130SAaron Sierra .name = "ICH9M",
433887c8ec7SAaron Sierra .iTCO_version = 2,
4344630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4354630b130SAaron Sierra },
4364630b130SAaron Sierra [LPC_ICH9ME] = {
4374630b130SAaron Sierra .name = "ICH9M-E",
438887c8ec7SAaron Sierra .iTCO_version = 2,
4394630b130SAaron Sierra .gpio_version = ICH_V9_GPIO,
4404630b130SAaron Sierra },
4414630b130SAaron Sierra [LPC_ICH10] = {
4424630b130SAaron Sierra .name = "ICH10",
443887c8ec7SAaron Sierra .iTCO_version = 2,
4444630b130SAaron Sierra .gpio_version = ICH_V10CONS_GPIO,
4454630b130SAaron Sierra },
4464630b130SAaron Sierra [LPC_ICH10R] = {
4474630b130SAaron Sierra .name = "ICH10R",
448887c8ec7SAaron Sierra .iTCO_version = 2,
4494630b130SAaron Sierra .gpio_version = ICH_V10CONS_GPIO,
4504630b130SAaron Sierra },
4514630b130SAaron Sierra [LPC_ICH10D] = {
4524630b130SAaron Sierra .name = "ICH10D",
453887c8ec7SAaron Sierra .iTCO_version = 2,
4544630b130SAaron Sierra .gpio_version = ICH_V10CORP_GPIO,
4554630b130SAaron Sierra },
4564630b130SAaron Sierra [LPC_ICH10DO] = {
4574630b130SAaron Sierra .name = "ICH10DO",
458887c8ec7SAaron Sierra .iTCO_version = 2,
4594630b130SAaron Sierra .gpio_version = ICH_V10CORP_GPIO,
4604630b130SAaron Sierra },
4614630b130SAaron Sierra [LPC_PCH] = {
4624630b130SAaron Sierra .name = "PCH Desktop Full Featured",
463887c8ec7SAaron Sierra .iTCO_version = 2,
4644630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4654630b130SAaron Sierra },
4664630b130SAaron Sierra [LPC_PCHM] = {
4674630b130SAaron Sierra .name = "PCH Mobile Full Featured",
468887c8ec7SAaron Sierra .iTCO_version = 2,
4694630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4704630b130SAaron Sierra },
4714630b130SAaron Sierra [LPC_P55] = {
4724630b130SAaron Sierra .name = "P55",
473887c8ec7SAaron Sierra .iTCO_version = 2,
4744630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4754630b130SAaron Sierra },
4764630b130SAaron Sierra [LPC_PM55] = {
4774630b130SAaron Sierra .name = "PM55",
478887c8ec7SAaron Sierra .iTCO_version = 2,
4794630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4804630b130SAaron Sierra },
4814630b130SAaron Sierra [LPC_H55] = {
4824630b130SAaron Sierra .name = "H55",
483887c8ec7SAaron Sierra .iTCO_version = 2,
4844630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4854630b130SAaron Sierra },
4864630b130SAaron Sierra [LPC_QM57] = {
4874630b130SAaron Sierra .name = "QM57",
488887c8ec7SAaron Sierra .iTCO_version = 2,
4894630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4904630b130SAaron Sierra },
4914630b130SAaron Sierra [LPC_H57] = {
4924630b130SAaron Sierra .name = "H57",
493887c8ec7SAaron Sierra .iTCO_version = 2,
4944630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
4954630b130SAaron Sierra },
4964630b130SAaron Sierra [LPC_HM55] = {
4974630b130SAaron Sierra .name = "HM55",
498887c8ec7SAaron Sierra .iTCO_version = 2,
4994630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5004630b130SAaron Sierra },
5014630b130SAaron Sierra [LPC_Q57] = {
5024630b130SAaron Sierra .name = "Q57",
503887c8ec7SAaron Sierra .iTCO_version = 2,
5044630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5054630b130SAaron Sierra },
5064630b130SAaron Sierra [LPC_HM57] = {
5074630b130SAaron Sierra .name = "HM57",
508887c8ec7SAaron Sierra .iTCO_version = 2,
5094630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5104630b130SAaron Sierra },
5114630b130SAaron Sierra [LPC_PCHMSFF] = {
5124630b130SAaron Sierra .name = "PCH Mobile SFF Full Featured",
513887c8ec7SAaron Sierra .iTCO_version = 2,
5144630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5154630b130SAaron Sierra },
5164630b130SAaron Sierra [LPC_QS57] = {
5174630b130SAaron Sierra .name = "QS57",
518887c8ec7SAaron Sierra .iTCO_version = 2,
5194630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5204630b130SAaron Sierra },
5214630b130SAaron Sierra [LPC_3400] = {
5224630b130SAaron Sierra .name = "3400",
523887c8ec7SAaron Sierra .iTCO_version = 2,
5244630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5254630b130SAaron Sierra },
5264630b130SAaron Sierra [LPC_3420] = {
5274630b130SAaron Sierra .name = "3420",
528887c8ec7SAaron Sierra .iTCO_version = 2,
5294630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5304630b130SAaron Sierra },
5314630b130SAaron Sierra [LPC_3450] = {
5324630b130SAaron Sierra .name = "3450",
533887c8ec7SAaron Sierra .iTCO_version = 2,
5344630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5354630b130SAaron Sierra },
5364630b130SAaron Sierra [LPC_EP80579] = {
5374630b130SAaron Sierra .name = "EP80579",
538887c8ec7SAaron Sierra .iTCO_version = 2,
5394630b130SAaron Sierra },
5404630b130SAaron Sierra [LPC_CPT] = {
5414630b130SAaron Sierra .name = "Cougar Point",
542887c8ec7SAaron Sierra .iTCO_version = 2,
5434630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5444630b130SAaron Sierra },
5454630b130SAaron Sierra [LPC_CPTD] = {
5464630b130SAaron Sierra .name = "Cougar Point Desktop",
547887c8ec7SAaron Sierra .iTCO_version = 2,
5484630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5494630b130SAaron Sierra },
5504630b130SAaron Sierra [LPC_CPTM] = {
5514630b130SAaron Sierra .name = "Cougar Point Mobile",
552887c8ec7SAaron Sierra .iTCO_version = 2,
5534630b130SAaron Sierra .gpio_version = ICH_V5_GPIO,
5544630b130SAaron Sierra },
5554630b130SAaron Sierra [LPC_PBG] = {
5564630b130SAaron Sierra .name = "Patsburg",
557887c8ec7SAaron Sierra .iTCO_version = 2,
5584630b130SAaron Sierra },
5594630b130SAaron Sierra [LPC_DH89XXCC] = {
5604630b130SAaron Sierra .name = "DH89xxCC",
561887c8ec7SAaron Sierra .iTCO_version = 2,
562ef0eea5bSChris Blake .gpio_version = ICH_V5_GPIO,
5634630b130SAaron Sierra },
5644630b130SAaron Sierra [LPC_PPT] = {
5654630b130SAaron Sierra .name = "Panther Point",
566887c8ec7SAaron Sierra .iTCO_version = 2,
56762cf2cdbSGuenter Roeck .gpio_version = ICH_V5_GPIO,
5684630b130SAaron Sierra },
5694630b130SAaron Sierra [LPC_LPT] = {
5704630b130SAaron Sierra .name = "Lynx Point",
571887c8ec7SAaron Sierra .iTCO_version = 2,
572e420d6a1SDan Gora .gpio_version = ICH_V5_GPIO,
573ff00d7a3SMika Westerberg .spi_type = INTEL_SPI_LPT,
5744630b130SAaron Sierra },
5757fb9c1a4SJames Ralston [LPC_LPT_LP] = {
5767fb9c1a4SJames Ralston .name = "Lynx Point_LP",
5777fb9c1a4SJames Ralston .iTCO_version = 2,
578ff00d7a3SMika Westerberg .spi_type = INTEL_SPI_LPT,
5797fb9c1a4SJames Ralston },
5806e6680e3SJames Ralston [LPC_WBG] = {
5816e6680e3SJames Ralston .name = "Wellsburg",
5826e6680e3SJames Ralston .iTCO_version = 2,
5836e6680e3SJames Ralston },
5848477128fSJames Ralston [LPC_AVN] = {
5858477128fSJames Ralston .name = "Avoton SoC",
586c48cf598SPeter Tyser .iTCO_version = 3,
587facd9939SVincent Donnefort .gpio_version = AVOTON_GPIO,
58807d70913SJoakim Tjernlund .spi_type = INTEL_SPI_BYT,
5898477128fSJames Ralston },
5906111ec70SPeter Tyser [LPC_BAYTRAIL] = {
5916111ec70SPeter Tyser .name = "Bay Trail SoC",
5926111ec70SPeter Tyser .iTCO_version = 3,
593ff00d7a3SMika Westerberg .spi_type = INTEL_SPI_BYT,
5946111ec70SPeter Tyser },
595283aae8aSSeth Heasley [LPC_COLETO] = {
596283aae8aSSeth Heasley .name = "Coleto Creek",
597283aae8aSSeth Heasley .iTCO_version = 2,
598283aae8aSSeth Heasley },
5995e90169cSJames Ralston [LPC_WPT_LP] = {
600a8822df9SJames Ralston .name = "Wildcat Point_LP",
6015e90169cSJames Ralston .iTCO_version = 2,
602ff00d7a3SMika Westerberg .spi_type = INTEL_SPI_LPT,
6035e90169cSJames Ralston },
604ff0c9da0SAlan Cox [LPC_BRASWELL] = {
605ff0c9da0SAlan Cox .name = "Braswell SoC",
606ff0c9da0SAlan Cox .iTCO_version = 3,
607ff00d7a3SMika Westerberg .spi_type = INTEL_SPI_BYT,
608ff0c9da0SAlan Cox },
6096223a309SAlexandra Yates [LPC_LEWISBURG] = {
6106223a309SAlexandra Yates .name = "Lewisburg",
6116223a309SAlexandra Yates .iTCO_version = 2,
6126223a309SAlexandra Yates },
613fea31042SJames Ralston [LPC_9S] = {
614fea31042SJames Ralston .name = "9 Series",
615fea31042SJames Ralston .iTCO_version = 2,
616e420d6a1SDan Gora .gpio_version = ICH_V5_GPIO,
617fea31042SJames Ralston },
61887eb832aSMika Westerberg [LPC_APL] = {
61987eb832aSMika Westerberg .name = "Apollo Lake SoC",
620e93c1021STan Jui Nee .iTCO_version = 5,
62187eb832aSMika Westerberg .spi_type = INTEL_SPI_BXT,
62287eb832aSMika Westerberg },
623a6450cb0SMika Westerberg [LPC_GLK] = {
624a6450cb0SMika Westerberg .name = "Gemini Lake SoC",
625a6450cb0SMika Westerberg .spi_type = INTEL_SPI_BXT,
626a6450cb0SMika Westerberg },
627f36c1f62SPriyalee Kushwaha [LPC_COUGARMOUNTAIN] = {
628f36c1f62SPriyalee Kushwaha .name = "Cougar Mountain SoC",
629f36c1f62SPriyalee Kushwaha .iTCO_version = 3,
630f36c1f62SPriyalee Kushwaha },
6314630b130SAaron Sierra };
6324630b130SAaron Sierra
6334630b130SAaron Sierra /*
6344630b130SAaron Sierra * This data only exists for exporting the supported PCI ids
6354630b130SAaron Sierra * via MODULE_DEVICE_TABLE. We do not actually register a
6364630b130SAaron Sierra * pci_driver, because the I/O Controller Hub has also other
6374630b130SAaron Sierra * functions that probably will be registered by other drivers.
6384630b130SAaron Sierra */
63936fcd06cSJingoo Han static const struct pci_device_id lpc_ich_ids[] = {
640aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
641aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
642aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
643aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
644aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
645aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
646aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
647aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
648aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
649aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
650aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
651aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
652aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
653aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
654aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
655aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
656aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
657aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
658aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
659aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
660aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
661aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
662aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
663aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
664aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
665aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
666aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
667aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
668aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
669aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
670aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
671aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
672aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
673aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
674aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
675aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
676aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
677aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
678aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
679aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
680aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
681aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
682aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
683aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
684aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
685aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
686aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
687aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
688aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
689aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
690aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
691aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
692aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
693aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
694aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
695aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
696aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
697aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
698aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
699aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
700aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
701aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
702aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
703aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
704aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
705aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
706aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
707aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
708aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
709aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
710aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
711aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
712aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
7134630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
7144630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
7154630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
7164630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
71772715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
7184630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
7194630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
7204630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
7214630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
7224630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
7234630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
7244630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
7254630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
7264630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
7274630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
7284630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
7294630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
7304630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
7314630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
7324630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
7334630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
7344630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
7354630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
7364630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
7374630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
7384630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
7394630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
7404630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
7414630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
7424630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
7434630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
74472715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
7454630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
7464630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
74772715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
7484630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
74972715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
7504630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
7514630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
7524630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
7534630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
7544630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
75572715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
7564630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
75772715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
75872715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
759a6450cb0SMika Westerberg { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
760f36c1f62SPriyalee Kushwaha { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
7614630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
76272715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
76372715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
76472715757SAndy Shevchenko { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
7654630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
7664630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
7674630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
7684630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
7694630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
7704630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
7714630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
7724630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
7734630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
7744630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
7754630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
7764630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
7774630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
7784630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
7794630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
7804630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
78187eb832aSMika Westerberg { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
7824630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
7834630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
7844630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
7854630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
7864630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
7874630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
7884630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
7894630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
7904630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
7914630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
7924630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
7934630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
7944630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
7954630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
7964630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
7974630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
7984630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
7994630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
8004630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
8014630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
8024630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
8034630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
8044630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
8054630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
8064630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
8074630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
8084630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
8094630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
8104630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
8114630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
8124630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
8134630b130SAaron Sierra { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
814aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
815aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
816aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
817aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
818aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
8196e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
8206e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
8216e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
8226e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
8236e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
8246e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
8256e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
8266e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
8276e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
8286e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
8296e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
8306e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
8316e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
8326e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
8336e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
8346e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
8356e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
8366e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
8376e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
8386e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
8396e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
8406e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
8416e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
8426e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
8436e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
8446e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
8456e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
8466e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
8476e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
8486e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
8496e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
8506e6680e3SJames Ralston { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
851aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
852aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
853aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
854aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
855aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
856aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
857aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
858aec9038eSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
8595e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
8605e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
8615e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
8625e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
8635e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
8645e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
8655e90169cSJames Ralston { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
8666223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
8676223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
8686223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
8696223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
8706223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
8716223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
8726223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
8736223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
8746223a309SAlexandra Yates { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
8754630b130SAaron Sierra { 0, }, /* End of list */
8764630b130SAaron Sierra };
8774630b130SAaron Sierra MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
8784630b130SAaron Sierra
lpc_ich_restore_config_space(struct pci_dev * dev)8794630b130SAaron Sierra static void lpc_ich_restore_config_space(struct pci_dev *dev)
8804630b130SAaron Sierra {
88101560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
88201560f6bSAaron Sierra
883eb71d4deSPeter Tyser if (priv->abase_save >= 0) {
884eb71d4deSPeter Tyser pci_write_config_byte(dev, priv->abase, priv->abase_save);
885eb71d4deSPeter Tyser priv->abase_save = -1;
886eb71d4deSPeter Tyser }
887eb71d4deSPeter Tyser
888eb71d4deSPeter Tyser if (priv->actrl_pbase_save >= 0) {
889eb71d4deSPeter Tyser pci_write_config_byte(dev, priv->actrl_pbase,
890eb71d4deSPeter Tyser priv->actrl_pbase_save);
891eb71d4deSPeter Tyser priv->actrl_pbase_save = -1;
8924630b130SAaron Sierra }
8934630b130SAaron Sierra
894429b941aSPeter Tyser if (priv->gctrl_save >= 0) {
895429b941aSPeter Tyser pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
896429b941aSPeter Tyser priv->gctrl_save = -1;
8974630b130SAaron Sierra }
8984630b130SAaron Sierra }
8994630b130SAaron Sierra
lpc_ich_enable_acpi_space(struct pci_dev * dev)900f791be49SBill Pemberton static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
9014630b130SAaron Sierra {
90201560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
9034630b130SAaron Sierra u8 reg_save;
9044630b130SAaron Sierra
905eb71d4deSPeter Tyser switch (lpc_chipset_info[priv->chipset].iTCO_version) {
906eb71d4deSPeter Tyser case 3:
907eb71d4deSPeter Tyser /*
908eb71d4deSPeter Tyser * Some chipsets (eg Avoton) enable the ACPI space in the
909eb71d4deSPeter Tyser * ACPI BASE register.
910eb71d4deSPeter Tyser */
911eb71d4deSPeter Tyser pci_read_config_byte(dev, priv->abase, ®_save);
912eb71d4deSPeter Tyser pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
913eb71d4deSPeter Tyser priv->abase_save = reg_save;
914eb71d4deSPeter Tyser break;
915eb71d4deSPeter Tyser default:
916eb71d4deSPeter Tyser /*
917eb71d4deSPeter Tyser * Most chipsets enable the ACPI space in the ACPI control
918eb71d4deSPeter Tyser * register.
919eb71d4deSPeter Tyser */
920eb71d4deSPeter Tyser pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
921eb71d4deSPeter Tyser pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
922eb71d4deSPeter Tyser priv->actrl_pbase_save = reg_save;
923eb71d4deSPeter Tyser break;
924eb71d4deSPeter Tyser }
9254630b130SAaron Sierra }
9264630b130SAaron Sierra
lpc_ich_enable_gpio_space(struct pci_dev * dev)927f791be49SBill Pemberton static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
9284630b130SAaron Sierra {
92901560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
9304630b130SAaron Sierra u8 reg_save;
9314630b130SAaron Sierra
932429b941aSPeter Tyser pci_read_config_byte(dev, priv->gctrl, ®_save);
933429b941aSPeter Tyser pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
934429b941aSPeter Tyser priv->gctrl_save = reg_save;
9354630b130SAaron Sierra }
9364630b130SAaron Sierra
lpc_ich_enable_pmc_space(struct pci_dev * dev)937eb71d4deSPeter Tyser static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
938eb71d4deSPeter Tyser {
939eb71d4deSPeter Tyser struct lpc_ich_priv *priv = pci_get_drvdata(dev);
940eb71d4deSPeter Tyser u8 reg_save;
941eb71d4deSPeter Tyser
942eb71d4deSPeter Tyser pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
943eb71d4deSPeter Tyser pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
944eb71d4deSPeter Tyser
945eb71d4deSPeter Tyser priv->actrl_pbase_save = reg_save;
946eb71d4deSPeter Tyser }
947eb71d4deSPeter Tyser
lpc_ich_finalize_wdt_cell(struct pci_dev * dev)948420b54deSMatt Fleming static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
949420b54deSMatt Fleming {
950420b54deSMatt Fleming struct itco_wdt_platform_data *pdata;
951420b54deSMatt Fleming struct lpc_ich_priv *priv = pci_get_drvdata(dev);
952420b54deSMatt Fleming struct lpc_ich_info *info;
9533dab794fSAaron Sierra struct mfd_cell *cell = &lpc_ich_wdt_cell;
954420b54deSMatt Fleming
955420b54deSMatt Fleming pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
956420b54deSMatt Fleming if (!pdata)
957420b54deSMatt Fleming return -ENOMEM;
958420b54deSMatt Fleming
959420b54deSMatt Fleming info = &lpc_chipset_info[priv->chipset];
960420b54deSMatt Fleming
961420b54deSMatt Fleming pdata->version = info->iTCO_version;
962*6a32d399SWolfram Sang strscpy(pdata->name, info->name, sizeof(pdata->name));
963420b54deSMatt Fleming
964420b54deSMatt Fleming cell->platform_data = pdata;
965420b54deSMatt Fleming cell->pdata_size = sizeof(*pdata);
966420b54deSMatt Fleming return 0;
967420b54deSMatt Fleming }
968420b54deSMatt Fleming
lpc_ich_finalize_gpio_cell(struct pci_dev * dev)969420b54deSMatt Fleming static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
9704630b130SAaron Sierra {
97101560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
9723dab794fSAaron Sierra struct mfd_cell *cell = &lpc_ich_gpio_cell;
97301560f6bSAaron Sierra
97401560f6bSAaron Sierra cell->platform_data = &lpc_chipset_info[priv->chipset];
9754630b130SAaron Sierra cell->pdata_size = sizeof(struct lpc_ich_info);
9764630b130SAaron Sierra }
9774630b130SAaron Sierra
9784f600adaSJean Delvare /*
9794f600adaSJean Delvare * We don't check for resource conflict globally. There are 2 or 3 independent
9804f600adaSJean Delvare * GPIO groups and it's enough to have access to one of these to instantiate
9814f600adaSJean Delvare * the device.
9824f600adaSJean Delvare */
lpc_ich_check_conflict_gpio(struct resource * res)983f791be49SBill Pemberton static int lpc_ich_check_conflict_gpio(struct resource *res)
9844f600adaSJean Delvare {
9854f600adaSJean Delvare int ret;
9864f600adaSJean Delvare u8 use_gpio = 0;
9874f600adaSJean Delvare
9884f600adaSJean Delvare if (resource_size(res) >= 0x50 &&
9894f600adaSJean Delvare !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
9904f600adaSJean Delvare use_gpio |= 1 << 2;
9914f600adaSJean Delvare
9924f600adaSJean Delvare if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
9934f600adaSJean Delvare use_gpio |= 1 << 1;
9944f600adaSJean Delvare
9954f600adaSJean Delvare ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
9964f600adaSJean Delvare if (!ret)
9974f600adaSJean Delvare use_gpio |= 1 << 0;
9984f600adaSJean Delvare
9994f600adaSJean Delvare return use_gpio ? use_gpio : ret;
10004f600adaSJean Delvare }
10014f600adaSJean Delvare
lpc_ich_init_gpio(struct pci_dev * dev)100201560f6bSAaron Sierra static int lpc_ich_init_gpio(struct pci_dev *dev)
10034630b130SAaron Sierra {
100401560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
10054630b130SAaron Sierra u32 base_addr_cfg;
10064630b130SAaron Sierra u32 base_addr;
10074630b130SAaron Sierra int ret;
10084630b130SAaron Sierra bool acpi_conflict = false;
10094630b130SAaron Sierra struct resource *res;
10104630b130SAaron Sierra
10114630b130SAaron Sierra /* Setup power management base register */
1012429b941aSPeter Tyser pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
10134630b130SAaron Sierra base_addr = base_addr_cfg & 0x0000ff80;
10144630b130SAaron Sierra if (!base_addr) {
10150c418844SPaul Bolle dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
10163dab794fSAaron Sierra lpc_ich_gpio_cell.num_resources--;
10174630b130SAaron Sierra goto gpe0_done;
10184630b130SAaron Sierra }
10194630b130SAaron Sierra
10204630b130SAaron Sierra res = &gpio_ich_res[ICH_RES_GPE0];
10214630b130SAaron Sierra res->start = base_addr + ACPIBASE_GPE_OFF;
10224630b130SAaron Sierra res->end = base_addr + ACPIBASE_GPE_END;
10234630b130SAaron Sierra ret = acpi_check_resource_conflict(res);
10244630b130SAaron Sierra if (ret) {
10254630b130SAaron Sierra /*
10264630b130SAaron Sierra * This isn't fatal for the GPIO, but we have to make sure that
10274630b130SAaron Sierra * the platform_device subsystem doesn't see this resource
10284630b130SAaron Sierra * or it will register an invalid region.
10294630b130SAaron Sierra */
10303dab794fSAaron Sierra lpc_ich_gpio_cell.num_resources--;
10314630b130SAaron Sierra acpi_conflict = true;
10324630b130SAaron Sierra } else {
10334630b130SAaron Sierra lpc_ich_enable_acpi_space(dev);
10344630b130SAaron Sierra }
10354630b130SAaron Sierra
10364630b130SAaron Sierra gpe0_done:
10374630b130SAaron Sierra /* Setup GPIO base register */
1038429b941aSPeter Tyser pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
10394630b130SAaron Sierra base_addr = base_addr_cfg & 0x0000ff80;
10404630b130SAaron Sierra if (!base_addr) {
10410c418844SPaul Bolle dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
10424630b130SAaron Sierra ret = -ENODEV;
10434630b130SAaron Sierra goto gpio_done;
10444630b130SAaron Sierra }
10454630b130SAaron Sierra
10464630b130SAaron Sierra /* Older devices provide fewer GPIO and have a smaller resource size. */
10474630b130SAaron Sierra res = &gpio_ich_res[ICH_RES_GPIO];
10484630b130SAaron Sierra res->start = base_addr;
104901560f6bSAaron Sierra switch (lpc_chipset_info[priv->chipset].gpio_version) {
10504630b130SAaron Sierra case ICH_V5_GPIO:
10514630b130SAaron Sierra case ICH_V10CORP_GPIO:
10524630b130SAaron Sierra res->end = res->start + 128 - 1;
10534630b130SAaron Sierra break;
10544630b130SAaron Sierra default:
10554630b130SAaron Sierra res->end = res->start + 64 - 1;
10564630b130SAaron Sierra break;
10574630b130SAaron Sierra }
10584630b130SAaron Sierra
10594f600adaSJean Delvare ret = lpc_ich_check_conflict_gpio(res);
10604f600adaSJean Delvare if (ret < 0) {
10614630b130SAaron Sierra /* this isn't necessarily fatal for the GPIO */
10624630b130SAaron Sierra acpi_conflict = true;
10634630b130SAaron Sierra goto gpio_done;
10644630b130SAaron Sierra }
106501560f6bSAaron Sierra lpc_chipset_info[priv->chipset].use_gpio = ret;
10664630b130SAaron Sierra lpc_ich_enable_gpio_space(dev);
10674630b130SAaron Sierra
1068420b54deSMatt Fleming lpc_ich_finalize_gpio_cell(dev);
10691abf25a2SMika Westerberg ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
10703dab794fSAaron Sierra &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
10714630b130SAaron Sierra
10724630b130SAaron Sierra gpio_done:
10734630b130SAaron Sierra if (acpi_conflict)
10744630b130SAaron Sierra pr_warn("Resource conflict(s) found affecting %s\n",
10753dab794fSAaron Sierra lpc_ich_gpio_cell.name);
10764630b130SAaron Sierra return ret;
10774630b130SAaron Sierra }
10784630b130SAaron Sierra
lpc_ich_init_wdt(struct pci_dev * dev)107901560f6bSAaron Sierra static int lpc_ich_init_wdt(struct pci_dev *dev)
1080887c8ec7SAaron Sierra {
108101560f6bSAaron Sierra struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1082887c8ec7SAaron Sierra u32 base_addr_cfg;
1083887c8ec7SAaron Sierra u32 base_addr;
1084887c8ec7SAaron Sierra int ret;
1085887c8ec7SAaron Sierra struct resource *res;
1086887c8ec7SAaron Sierra
10873413f702SMika Westerberg /* If we have ACPI based watchdog use that instead */
10883413f702SMika Westerberg if (acpi_has_watchdog())
10893413f702SMika Westerberg return -ENODEV;
10903413f702SMika Westerberg
1091887c8ec7SAaron Sierra /* Setup power management base register */
1092429b941aSPeter Tyser pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1093887c8ec7SAaron Sierra base_addr = base_addr_cfg & 0x0000ff80;
1094887c8ec7SAaron Sierra if (!base_addr) {
10950c418844SPaul Bolle dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1096887c8ec7SAaron Sierra ret = -ENODEV;
1097887c8ec7SAaron Sierra goto wdt_done;
1098887c8ec7SAaron Sierra }
1099887c8ec7SAaron Sierra
1100887c8ec7SAaron Sierra res = wdt_io_res(ICH_RES_IO_TCO);
1101887c8ec7SAaron Sierra res->start = base_addr + ACPIBASE_TCO_OFF;
1102887c8ec7SAaron Sierra res->end = base_addr + ACPIBASE_TCO_END;
1103887c8ec7SAaron Sierra
1104887c8ec7SAaron Sierra res = wdt_io_res(ICH_RES_IO_SMI);
1105887c8ec7SAaron Sierra res->start = base_addr + ACPIBASE_SMI_OFF;
1106887c8ec7SAaron Sierra res->end = base_addr + ACPIBASE_SMI_END;
1107092369efSFeng Tang
1108887c8ec7SAaron Sierra lpc_ich_enable_acpi_space(dev);
1109887c8ec7SAaron Sierra
1110887c8ec7SAaron Sierra /*
1111eb71d4deSPeter Tyser * iTCO v2:
1112887c8ec7SAaron Sierra * Get the Memory-Mapped GCS register. To get access to it
1113887c8ec7SAaron Sierra * we have to read RCBA from PCI Config space 0xf0 and use
1114887c8ec7SAaron Sierra * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1115eb71d4deSPeter Tyser *
1116eb71d4deSPeter Tyser * iTCO v3:
1117eb71d4deSPeter Tyser * Get the Power Management Configuration register. To get access
1118eb71d4deSPeter Tyser * to it we have to read the PMC BASE from config space and address
1119eb71d4deSPeter Tyser * the register at offset 0x8.
1120887c8ec7SAaron Sierra */
112101560f6bSAaron Sierra if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1122e294bc91SPeter Hurley /* Don't register iomem for TCO ver 1 */
11233dab794fSAaron Sierra lpc_ich_wdt_cell.num_resources--;
1124eb71d4deSPeter Tyser } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1125887c8ec7SAaron Sierra pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1126887c8ec7SAaron Sierra base_addr = base_addr_cfg & 0xffffc000;
1127887c8ec7SAaron Sierra if (!(base_addr_cfg & 1)) {
11280c418844SPaul Bolle dev_notice(&dev->dev, "RCBA is disabled by "
11290c418844SPaul Bolle "hardware/BIOS, device disabled\n");
1130887c8ec7SAaron Sierra ret = -ENODEV;
1131887c8ec7SAaron Sierra goto wdt_done;
1132887c8ec7SAaron Sierra }
1133eb71d4deSPeter Tyser res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1134887c8ec7SAaron Sierra res->start = base_addr + ACPIBASE_GCS_OFF;
1135887c8ec7SAaron Sierra res->end = base_addr + ACPIBASE_GCS_END;
1136eb71d4deSPeter Tyser } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1137eb71d4deSPeter Tyser lpc_ich_enable_pmc_space(dev);
1138eb71d4deSPeter Tyser pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1139eb71d4deSPeter Tyser base_addr = base_addr_cfg & 0xfffffe00;
1140eb71d4deSPeter Tyser
1141eb71d4deSPeter Tyser res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1142eb71d4deSPeter Tyser res->start = base_addr + ACPIBASE_PMC_OFF;
1143eb71d4deSPeter Tyser res->end = base_addr + ACPIBASE_PMC_END;
1144887c8ec7SAaron Sierra }
1145887c8ec7SAaron Sierra
1146420b54deSMatt Fleming ret = lpc_ich_finalize_wdt_cell(dev);
1147420b54deSMatt Fleming if (ret)
1148420b54deSMatt Fleming goto wdt_done;
1149420b54deSMatt Fleming
11501abf25a2SMika Westerberg ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
11513dab794fSAaron Sierra &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1152887c8ec7SAaron Sierra
1153887c8ec7SAaron Sierra wdt_done:
1154887c8ec7SAaron Sierra return ret;
1155887c8ec7SAaron Sierra }
1156887c8ec7SAaron Sierra
lpc_ich_init_pinctrl(struct pci_dev * dev)11577064d7d8STan Jui Nee static int lpc_ich_init_pinctrl(struct pci_dev *dev)
11587064d7d8STan Jui Nee {
11597064d7d8STan Jui Nee struct resource base;
11607064d7d8STan Jui Nee unsigned int i;
11617064d7d8STan Jui Nee int ret;
11627064d7d8STan Jui Nee
11637064d7d8STan Jui Nee /* Check, if GPIO has been exported as an ACPI device */
11647064d7d8STan Jui Nee if (acpi_dev_present("INT3452", NULL, -1))
11657064d7d8STan Jui Nee return -EEXIST;
11667064d7d8STan Jui Nee
11677064d7d8STan Jui Nee ret = p2sb_bar(dev->bus, 0, &base);
11687064d7d8STan Jui Nee if (ret)
11697064d7d8STan Jui Nee return ret;
11707064d7d8STan Jui Nee
11717064d7d8STan Jui Nee for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
11727064d7d8STan Jui Nee struct resource *mem = &apl_gpio_resources[i][0];
11737064d7d8STan Jui Nee resource_size_t offset = apl_gpio_offsets[i];
11747064d7d8STan Jui Nee
11757064d7d8STan Jui Nee /* Fill MEM resource */
11767064d7d8STan Jui Nee mem->start = base.start + offset;
11777064d7d8STan Jui Nee mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1;
11787064d7d8STan Jui Nee mem->flags = base.flags;
11797064d7d8STan Jui Nee }
11807064d7d8STan Jui Nee
11817064d7d8STan Jui Nee return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
11827064d7d8STan Jui Nee ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
11837064d7d8STan Jui Nee }
11847064d7d8STan Jui Nee
lpc_ich_byt_set_writeable(void __iomem * base,void * data)1185cd149effSMika Westerberg static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1186cd149effSMika Westerberg {
1187cd149effSMika Westerberg u32 val;
1188cd149effSMika Westerberg
1189cd149effSMika Westerberg val = readl(base + BYT_BCR);
1190cd149effSMika Westerberg if (!(val & BYT_BCR_WPD)) {
1191cd149effSMika Westerberg val |= BYT_BCR_WPD;
1192cd149effSMika Westerberg writel(val, base + BYT_BCR);
1193cd149effSMika Westerberg val = readl(base + BYT_BCR);
1194cd149effSMika Westerberg }
1195cd149effSMika Westerberg
1196cd149effSMika Westerberg return val & BYT_BCR_WPD;
1197cd149effSMika Westerberg }
1198cd149effSMika Westerberg
lpc_ich_set_writeable(struct pci_bus * bus,unsigned int devfn)11996e3b29dbSAndy Shevchenko static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)
1200cd149effSMika Westerberg {
1201cd149effSMika Westerberg u32 bcr;
1202cd149effSMika Westerberg
12036e3b29dbSAndy Shevchenko pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1204cd149effSMika Westerberg if (!(bcr & BCR_WPD)) {
1205cd149effSMika Westerberg bcr |= BCR_WPD;
12066e3b29dbSAndy Shevchenko pci_bus_write_config_dword(bus, devfn, BCR, bcr);
12076e3b29dbSAndy Shevchenko pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1208cd149effSMika Westerberg }
1209cd149effSMika Westerberg
1210cd149effSMika Westerberg return bcr & BCR_WPD;
1211cd149effSMika Westerberg }
1212cd149effSMika Westerberg
lpc_ich_lpt_set_writeable(void __iomem * base,void * data)12136e3b29dbSAndy Shevchenko static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
12146e3b29dbSAndy Shevchenko {
12156e3b29dbSAndy Shevchenko struct pci_dev *pdev = data;
12166e3b29dbSAndy Shevchenko
12176e3b29dbSAndy Shevchenko return lpc_ich_set_writeable(pdev->bus, pdev->devfn);
12186e3b29dbSAndy Shevchenko }
12196e3b29dbSAndy Shevchenko
lpc_ich_bxt_set_writeable(void __iomem * base,void * data)1220cd149effSMika Westerberg static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1221cd149effSMika Westerberg {
12226e3b29dbSAndy Shevchenko struct pci_dev *pdev = data;
1223cd149effSMika Westerberg
12246e3b29dbSAndy Shevchenko return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));
1225cd149effSMika Westerberg }
1226cd149effSMika Westerberg
lpc_ich_init_spi(struct pci_dev * dev)1227ff00d7a3SMika Westerberg static int lpc_ich_init_spi(struct pci_dev *dev)
1228ff00d7a3SMika Westerberg {
1229ff00d7a3SMika Westerberg struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1230ff00d7a3SMika Westerberg struct resource *res = &intel_spi_res[0];
1231ff00d7a3SMika Westerberg struct intel_spi_boardinfo *info;
1232cd149effSMika Westerberg u32 spi_base, rcba;
123355979319SAndy Shevchenko int ret;
1234ff00d7a3SMika Westerberg
1235ff00d7a3SMika Westerberg info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1236ff00d7a3SMika Westerberg if (!info)
1237ff00d7a3SMika Westerberg return -ENOMEM;
1238ff00d7a3SMika Westerberg
1239ff00d7a3SMika Westerberg info->type = lpc_chipset_info[priv->chipset].spi_type;
1240ff00d7a3SMika Westerberg
1241ff00d7a3SMika Westerberg switch (info->type) {
1242ff00d7a3SMika Westerberg case INTEL_SPI_BYT:
1243ff00d7a3SMika Westerberg pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1244ff00d7a3SMika Westerberg if (spi_base & SPIBASE_BYT_EN) {
1245ff00d7a3SMika Westerberg res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1246ff00d7a3SMika Westerberg res->end = res->start + SPIBASE_BYT_SZ - 1;
1247cd149effSMika Westerberg
1248cd149effSMika Westerberg info->set_writeable = lpc_ich_byt_set_writeable;
1249ff00d7a3SMika Westerberg }
1250ff00d7a3SMika Westerberg break;
1251ff00d7a3SMika Westerberg
1252ff00d7a3SMika Westerberg case INTEL_SPI_LPT:
1253ff00d7a3SMika Westerberg pci_read_config_dword(dev, RCBABASE, &rcba);
1254ff00d7a3SMika Westerberg if (rcba & 1) {
1255ff00d7a3SMika Westerberg spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1256ff00d7a3SMika Westerberg res->start = spi_base + SPIBASE_LPT;
1257ff00d7a3SMika Westerberg res->end = res->start + SPIBASE_LPT_SZ - 1;
1258ff00d7a3SMika Westerberg
1259cd149effSMika Westerberg info->set_writeable = lpc_ich_lpt_set_writeable;
1260cd149effSMika Westerberg info->data = dev;
1261ff00d7a3SMika Westerberg }
1262ff00d7a3SMika Westerberg break;
1263ff00d7a3SMika Westerberg
126455979319SAndy Shevchenko case INTEL_SPI_BXT:
126587eb832aSMika Westerberg /*
126687eb832aSMika Westerberg * The P2SB is hidden by BIOS and we need to unhide it in
126787eb832aSMika Westerberg * order to read BAR of the SPI flash device. Once that is
126887eb832aSMika Westerberg * done we hide it again.
126987eb832aSMika Westerberg */
127055979319SAndy Shevchenko ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
127155979319SAndy Shevchenko if (ret)
127255979319SAndy Shevchenko return ret;
127387eb832aSMika Westerberg
1274cd149effSMika Westerberg info->set_writeable = lpc_ich_bxt_set_writeable;
12756e3b29dbSAndy Shevchenko info->data = dev;
127687eb832aSMika Westerberg break;
127787eb832aSMika Westerberg
1278ff00d7a3SMika Westerberg default:
1279ff00d7a3SMika Westerberg return -EINVAL;
1280ff00d7a3SMika Westerberg }
1281ff00d7a3SMika Westerberg
1282ff00d7a3SMika Westerberg if (!res->start)
1283ff00d7a3SMika Westerberg return -ENODEV;
1284ff00d7a3SMika Westerberg
1285ff00d7a3SMika Westerberg lpc_ich_spi_cell.platform_data = info;
1286ff00d7a3SMika Westerberg lpc_ich_spi_cell.pdata_size = sizeof(*info);
1287ff00d7a3SMika Westerberg
1288ff00d7a3SMika Westerberg return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1289ff00d7a3SMika Westerberg &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1290ff00d7a3SMika Westerberg }
1291ff00d7a3SMika Westerberg
lpc_ich_probe(struct pci_dev * dev,const struct pci_device_id * id)1292f791be49SBill Pemberton static int lpc_ich_probe(struct pci_dev *dev,
12934630b130SAaron Sierra const struct pci_device_id *id)
12944630b130SAaron Sierra {
129501560f6bSAaron Sierra struct lpc_ich_priv *priv;
12964630b130SAaron Sierra int ret;
12974630b130SAaron Sierra bool cell_added = false;
12984630b130SAaron Sierra
1299ff7109faSAaron Sierra priv = devm_kzalloc(&dev->dev,
1300ff7109faSAaron Sierra sizeof(struct lpc_ich_priv), GFP_KERNEL);
130101560f6bSAaron Sierra if (!priv)
130201560f6bSAaron Sierra return -ENOMEM;
130301560f6bSAaron Sierra
130401560f6bSAaron Sierra priv->chipset = id->driver_data;
130501560f6bSAaron Sierra
1306eb71d4deSPeter Tyser priv->actrl_pbase_save = -1;
1307eb71d4deSPeter Tyser priv->abase_save = -1;
1308eb71d4deSPeter Tyser
1309429b941aSPeter Tyser priv->abase = ACPIBASE;
1310eb71d4deSPeter Tyser priv->actrl_pbase = ACPICTRL_PMCBASE;
1311429b941aSPeter Tyser
1312429b941aSPeter Tyser priv->gctrl_save = -1;
131301560f6bSAaron Sierra if (priv->chipset <= LPC_ICH5) {
1314429b941aSPeter Tyser priv->gbase = GPIOBASE_ICH0;
1315429b941aSPeter Tyser priv->gctrl = GPIOCTRL_ICH0;
131601560f6bSAaron Sierra } else {
1317429b941aSPeter Tyser priv->gbase = GPIOBASE_ICH6;
1318429b941aSPeter Tyser priv->gctrl = GPIOCTRL_ICH6;
131901560f6bSAaron Sierra }
132001560f6bSAaron Sierra
132101560f6bSAaron Sierra pci_set_drvdata(dev, priv);
132201560f6bSAaron Sierra
1323f0776b8cSPeter Tyser if (lpc_chipset_info[priv->chipset].iTCO_version) {
132401560f6bSAaron Sierra ret = lpc_ich_init_wdt(dev);
1325887c8ec7SAaron Sierra if (!ret)
1326887c8ec7SAaron Sierra cell_added = true;
1327f0776b8cSPeter Tyser }
1328887c8ec7SAaron Sierra
1329f0776b8cSPeter Tyser if (lpc_chipset_info[priv->chipset].gpio_version) {
133001560f6bSAaron Sierra ret = lpc_ich_init_gpio(dev);
13314630b130SAaron Sierra if (!ret)
13324630b130SAaron Sierra cell_added = true;
1333f0776b8cSPeter Tyser }
13344630b130SAaron Sierra
13357064d7d8STan Jui Nee if (priv->chipset == LPC_APL) {
13367064d7d8STan Jui Nee ret = lpc_ich_init_pinctrl(dev);
13377064d7d8STan Jui Nee if (!ret)
13387064d7d8STan Jui Nee cell_added = true;
13397064d7d8STan Jui Nee }
13407064d7d8STan Jui Nee
1341ff00d7a3SMika Westerberg if (lpc_chipset_info[priv->chipset].spi_type) {
1342ff00d7a3SMika Westerberg ret = lpc_ich_init_spi(dev);
1343ff00d7a3SMika Westerberg if (!ret)
1344ff00d7a3SMika Westerberg cell_added = true;
1345ff00d7a3SMika Westerberg }
1346ff00d7a3SMika Westerberg
13474630b130SAaron Sierra /*
13484630b130SAaron Sierra * We only care if at least one or none of the cells registered
13494630b130SAaron Sierra * successfully.
13504630b130SAaron Sierra */
13514630b130SAaron Sierra if (!cell_added) {
13520c418844SPaul Bolle dev_warn(&dev->dev, "No MFD cells added\n");
13534630b130SAaron Sierra lpc_ich_restore_config_space(dev);
13544630b130SAaron Sierra return -ENODEV;
13554630b130SAaron Sierra }
13564630b130SAaron Sierra
13574630b130SAaron Sierra return 0;
13584630b130SAaron Sierra }
13594630b130SAaron Sierra
lpc_ich_remove(struct pci_dev * dev)13604740f73fSBill Pemberton static void lpc_ich_remove(struct pci_dev *dev)
13614630b130SAaron Sierra {
13624630b130SAaron Sierra mfd_remove_devices(&dev->dev);
13634630b130SAaron Sierra lpc_ich_restore_config_space(dev);
13644630b130SAaron Sierra }
13654630b130SAaron Sierra
13664630b130SAaron Sierra static struct pci_driver lpc_ich_driver = {
13674630b130SAaron Sierra .name = "lpc_ich",
13684630b130SAaron Sierra .id_table = lpc_ich_ids,
13694630b130SAaron Sierra .probe = lpc_ich_probe,
137084449216SBill Pemberton .remove = lpc_ich_remove,
13714630b130SAaron Sierra };
13724630b130SAaron Sierra
1373b4d0fe9cSLibo Chen module_pci_driver(lpc_ich_driver);
13744630b130SAaron Sierra
13754630b130SAaron Sierra MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
13764630b130SAaron Sierra MODULE_DESCRIPTION("LPC interface for Intel ICH");
13774630b130SAaron Sierra MODULE_LICENSE("GPL");
1378