Searched refs:cfsr (Results 1 – 5 of 5) sorted by relevance
246 env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; in v7m_stack_write()250 env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; in v7m_stack_write()263 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()266 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; in v7m_stack_write()325 env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK; in v7m_stack_read()337 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; in v7m_stack_read()382 env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; in HELPER()386 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in HELPER()806 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_callee_stack()1239 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_stack()[all …]
37 uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */ member
540 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),738 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
600 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ member
2308 val = s->cpu->env.v7m.cfsr[attrs.secure]; in nvic_sysreg_read()2313 val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; in nvic_sysreg_read()2442 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; in nvic_sysreg_write()2447 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); in nvic_sysreg_write()