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Searched refs:cfgr (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/gpio/
H A Datmel_pio4.c63 writel(reg, &port_base->cfgr); in atmel_pio4_config_io_func()
140 writel(reg, &port_base->cfgr); in atmel_pio4_set_pio_output()
166 writel(reg, &port_base->cfgr); in atmel_pio4_get_pio_input()
201 clrbits_le32(&port_base->cfgr, in atmel_pio4_direction_input()
217 clrsetbits_le32(&port_base->cfgr, in atmel_pio4_direction_output()
263 return (readl(&port_base->cfgr) & in atmel_pio4_get_function()
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c153 writel(0, &regs->cfgr); /* Reset CFGR */ in configure_clocks()
165 setbits_le32(&regs->cfgr, (( in configure_clocks()
249 clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
250 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
252 while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
354 (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK) in stm32_get_apb_shift()
358 (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK) in stm32_get_apb_shift()
403 if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == in stm32_clk_get_rate()
H A Dclk_stm32h7.c124 u32 cfgr; /* 0x10 Clock Configuration Register */ member
360 writel(0, &regs->cfgr); in configure_clocks()
417 clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); in configure_clocks()
418 while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) in configure_clocks()
596 if (readl(&regs->cfgr) & RCC_CFGR_TIMPRE) in stm32_get_timer_rate()
644 source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK; in stm32_clk_get_rate()
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c451 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) { in rcc_update_cr_register()
471 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && in rcc_update_cr_register()
495 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 || in rcc_update_cr_register()
522 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 || in rcc_update_cr_register()
549 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE); in rcc_update_cfgr_register()
561 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL); in rcc_update_cfgr_register()
581 val = FIELD_EX32(s->cfgr, CFGR, PPRE2); in rcc_update_cfgr_register()
591 val = FIELD_EX32(s->cfgr, CFGR, PPRE1); in rcc_update_cfgr_register()
601 val = FIELD_EX32(s->cfgr, CFGR, HPRE); in rcc_update_cfgr_register()
611 val = FIELD_EX32(s->cfgr, CFGR, SW); in rcc_update_cfgr_register()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_mc.h20 u32 cfgr; /* 0x04 Configuration Register */ member
H A Datmel_pio4.h14 u32 cfgr; /* 0x04 PIO Configuration Register */ member
/openbmc/u-boot/include/
H A Dstm32_rcc.h62 u32 cfgr; /* RCC clock configuration */ member
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h189 uint32_t cfgr; member
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c144 writel(conf, &bank_base->cfgr); in atmel_pinctrl_set_state()