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Searched refs:cfg_base (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/pci/
H A Dpci-rcar-gen2.c87 fdt_addr_t cfg_base; member
114 return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3); in get_bus_address()
124 writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG); in setup_bus_address()
185 clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG, in rcar_gen2_pci_probe()
189 clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST); in rcar_gen2_pci_probe()
192 writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); in rcar_gen2_pci_probe()
194 priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); in rcar_gen2_pci_probe()
196 priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); in rcar_gen2_pci_probe()
198 priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG); in rcar_gen2_pci_probe()
199 setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG, in rcar_gen2_pci_probe()
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H A Dpcie_xilinx.c19 void *cfg_base; member
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
76 addr = pcie->cfg_base; in pcie_xilinx_config_address()
154 pcie->cfg_base = map_physmem(reg_res.start, in pcie_xilinx_ofdata_to_platdata()
H A Dpcie_ecam_generic.c21 void *cfg_base; member
44 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
118 pcie->cfg_base = map_physmem(reg_res.start, in pci_generic_ecam_ofdata_to_platdata()
H A Dpcie_dw_mvebu.c110 void *cfg_base; member
198 atu_type, (u64)pcie->cfg_base, in set_cfg_address()
200 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
556 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, in pcie_dw_mvebu_ofdata_to_platdata()
558 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) in pcie_dw_mvebu_ofdata_to_platdata()
/openbmc/qemu/include/hw/pci-host/
H A Dxilinx-pcie.h49 uint64_t cfg_base, cfg_size; member
/openbmc/qemu/hw/ppc/
H A Dppc440_uc.c744 uint64_t cfg_base; member
793 ret = s->cfg_base >> 32; in dcr_read_pcie()
796 ret = s->cfg_base; in dcr_read_pcie()
873 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); in dcr_write_pcie()
876 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
889 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); in dcr_write_pcie()
/openbmc/qemu/hw/pci-host/
H A Dxilinx-pcie.c161 DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),