| /openbmc/linux/drivers/gpu/drm/v3d/ |
| H A D | v3d_trace.h | 187 TP_PROTO(struct drm_device *dev, u32 cfg5, u32 cfg6),
188 TP_ARGS(dev, cfg5, cfg6),
192 __field(u32, cfg5)
198 __entry->cfg5 = cfg5;
204 __entry->cfg5,
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| /openbmc/qemu/hw/misc/ |
| H A D | mps2-scc.c | 189 r = s->cfg5; in mps2_scc_read()
287 s->cfg5 = value; in mps2_scc_write()
369 s->cfg5 = 0; in mps2_scc_reset()
442 VMSTATE_UINT32(cfg5, MPS2SCC),
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| /openbmc/qemu/include/hw/misc/ |
| H A D | mps2-scc.h | 52 uint32_t cfg5; member
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| /openbmc/linux/arch/mips/kvm/ |
| H A D | mips.c | 1375 unsigned int sr, cfg5; in kvm_own_fpu() local
1397 cfg5 = kvm_read_c0_guest_config5(cop0); in kvm_own_fpu()
1398 change_c0_config5(MIPS_CONF5_FRE, cfg5); in kvm_own_fpu()
1419 unsigned int sr, cfg5; in kvm_own_msa() local
1441 cfg5 = kvm_read_c0_guest_config5(cop0); in kvm_own_msa()
1442 change_c0_config5(MIPS_CONF5_FRE, cfg5); in kvm_own_msa()
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| /openbmc/linux/drivers/hwmon/ |
| H A D | lm85.c | 59 ((data)->type == adt7468 && !((data)->cfg5 & ADT7468_OFF64))
61 ((data)->type == adt7468 && !((data)->cfg5 & ADT7468_HFPWM))
316 u8 cfg5; /* Config Register 5 on ADT7468 */ member
417 data->cfg5 = lm85_read_value(client, ADT7468_REG_CFG5); in lm85_update_device()
814 data->cfg5 &= ~ADT7468_HFPWM; in pwm_freq_store()
815 lm85_write_value(client, ADT7468_REG_CFG5, data->cfg5); in pwm_freq_store()
823 data->cfg5 |= ADT7468_HFPWM; in pwm_freq_store()
824 lm85_write_value(client, ADT7468_REG_CFG5, data->cfg5); in pwm_freq_store()
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | tegra210-emc-core.c | 1224 u32 cmd_pad, dq_pad, rfu1, cfg5, common_tx, ramp_up_wait = 0; in tegra210_emc_dvfs_power_ramp_up() local
1235 cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1313 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1319 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1325 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1339 u32 ramp_down_wait = 0, cmd_pad, dq_pad, rfu1, cfg5, common_tx; in tegra210_emc_dvfs_power_ramp_down() local
1351 cfg5 = entry->burst_regs[EMC_FBIO_CFG5_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1357 ccfifo_writel(emc, cfg5 | EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_down()
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| /openbmc/linux/drivers/net/ethernet/realtek/ |
| H A D | 8139too.c | 2314 u8 cfg5 = RTL_R8 (Config5); in rtl8139_get_wol() local
2326 if (cfg5 & Cfg5_UWF) in rtl8139_get_wol()
2328 if (cfg5 & Cfg5_MWF) in rtl8139_get_wol()
2330 if (cfg5 & Cfg5_BWF) in rtl8139_get_wol()
2345 u8 cfg3, cfg5; in rtl8139_set_wol() local
2364 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); in rtl8139_set_wol()
2369 cfg5 |= Cfg5_UWF; in rtl8139_set_wol()
2371 cfg5 |= Cfg5_MWF; in rtl8139_set_wol()
2373 cfg5 |= Cfg5_BWF; in rtl8139_set_wol()
2374 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ in rtl8139_set_wol()
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
| H A D | imx-regs.h | 771 u32 cfg5; member
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| /openbmc/linux/drivers/net/ethernet/broadcom/ |
| H A D | tg3.c | 15174 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0; in tg3_get_eeprom_hw_cfg() local
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15350 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV) in tg3_get_eeprom_hw_cfg()
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