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Searched refs:ccr (Results 1 – 25 of 168) sorted by relevance

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/openbmc/u-boot/drivers/rtc/
H A Dm48t35ax.c27 uchar ccr; /* Clock control register */ in rtc_get() local
30 ccr = rtc_read(0); in rtc_get()
31 ccr = ccr | 0x40; in rtc_get()
32 rtc_write(0, ccr); in rtc_get()
43 ccr = rtc_read(0); in rtc_get()
44 ccr = ccr & 0xBF; in rtc_get()
45 rtc_write(0, ccr); in rtc_get()
71 uchar ccr; /* Clock control register */ in rtc_set() local
79 ccr = rtc_read(0); in rtc_set()
80 ccr = ccr | 0x80; in rtc_set()
[all …]
/openbmc/linux/drivers/net/can/sja1000/
H A Dpeak_pcmcia.c140 u8 ccr; member
223 if (card->ccr == v) in pcan_write_reg()
225 card->ccr = v; in pcan_write_reg()
343 u8 ccr = card->ccr; in pcan_set_leds() local
349 ccr &= ~PCC_CCR_LED_MASK_CHAN(i); in pcan_set_leds()
351 ccr |= PCC_CCR_LED_CHAN(state, i); in pcan_set_leds()
355 pcan_write_reg(card, PCC_CCR, ccr); in pcan_set_leds()
380 u8 ccr; in pcan_led_timer() local
382 ccr = card->ccr; in pcan_led_timer()
385 ccr &= ~PCC_CCR_LED_MASK_CHAN(i); in pcan_led_timer()
[all …]
/openbmc/linux/arch/powerpc/math-emu/
H A Dmcrfs.c10 mcrfs(u32 *ccr, u32 crfD, u32 crfS) in mcrfs() argument
15 printk("%s: %p (%08x) %d %d\n", __func__, ccr, *ccr, crfD, crfS); in mcrfs()
25 *ccr &= ~(15 << ((7 - crfD) << 2)); in mcrfs()
26 *ccr |= (value << ((7 - crfD) << 2)); in mcrfs()
29 printk("CR: %08x\n", __func__, *ccr); in mcrfs()
H A Dfcmpu.c11 fcmpu(u32 *ccr, int crfD, void *frA, void *frB) in fcmpu() argument
20 printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB); in fcmpu()
37 *ccr &= ~(15 << ((7 - crfD) << 2)); in fcmpu()
38 *ccr |= (cmp << ((7 - crfD) << 2)); in fcmpu()
41 printk("CR: %08x\n", *ccr); in fcmpu()
H A Dfcmpo.c11 fcmpo(u32 *ccr, int crfD, void *frA, void *frB) in fcmpo() argument
20 printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB); in fcmpo()
40 *ccr &= ~(15 << ((7 - crfD) << 2)); in fcmpo()
41 *ccr |= (cmp << ((7 - crfD) << 2)); in fcmpo()
44 printk("CR: %08x\n", *ccr); in fcmpo()
/openbmc/linux/drivers/mtd/nand/raw/
H A Dndfc.c44 uint32_t ccr; in ndfc_select_chip() local
47 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); in ndfc_select_chip()
49 ccr &= ~NDFC_CCR_BS_MASK; in ndfc_select_chip()
50 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); in ndfc_select_chip()
52 ccr |= NDFC_CCR_RESET_CE; in ndfc_select_chip()
53 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); in ndfc_select_chip()
78 uint32_t ccr; in ndfc_enable_hwecc() local
81 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); in ndfc_enable_hwecc()
82 ccr |= NDFC_CCR_RESET_ECC; in ndfc_enable_hwecc()
83 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); in ndfc_enable_hwecc()
[all …]
/openbmc/linux/arch/sh/mm/
H A Dcache-shx3.c20 unsigned int ccr; in shx3_cache_init() local
22 ccr = __raw_readl(SH_CCR); in shx3_cache_init()
28 ccr |= CCR_CACHE_SNM; in shx3_cache_init()
40 ccr |= CCR_CACHE_IBE; in shx3_cache_init()
43 writel_uncached(ccr, SH_CCR); in shx3_cache_init()
H A Dcache-debugfs.c30 unsigned long ccr; in cache_debugfs_show() local
39 ccr = __raw_readl(SH_CCR); in cache_debugfs_show()
40 if ((ccr & CCR_CACHE_ENABLE) == 0) { in cache_debugfs_show()
61 if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE) in cache_debugfs_show()
H A Dcache-sh2.c60 unsigned long ccr; in sh2__flush_invalidate_region() local
65 ccr = __raw_readl(SH_CCR); in sh2__flush_invalidate_region()
66 ccr |= CCR_CACHE_INVALIDATE; in sh2__flush_invalidate_region()
67 __raw_writel(ccr, SH_CCR); in sh2__flush_invalidate_region()
/openbmc/linux/drivers/dma/
H A Dtxx9dmac.h167 u32 ccr; member
239 return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0; in txx9dmac_chan_INTENT()
244 dc->ccr |= TXX9_DMA_CCR_INTENT; in txx9dmac_chan_set_INTENT()
254 dc->ccr |= TXX9_DMA_CCR_SMPCHN; in txx9dmac_chan_set_SMPCHN()
259 u32 sair, u32 dair, u32 ccr) in txx9dmac_desc_set_nosimple() argument
289 u32 sai, u32 dai, u32 ccr) in txx9dmac_desc_set_nosimple() argument
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
H A Dstm32-mdma.c224 u32 ccr; member
408 u32 ccr, cisr, id, reg; in stm32_mdma_disable_chan() local
417 ccr = stm32_mdma_read(dmadev, reg); in stm32_mdma_disable_chan()
418 if (ccr & STM32_MDMA_CCR_EN) { in stm32_mdma_disable_chan()
485 u32 ccr, ctcr, ctbr, tlen; in stm32_mdma_set_xfer_param() local
492 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; in stm32_mdma_set_xfer_param()
535 ccr &= ~(STM32_MDMA_CCR_SWRQ | STM32_MDMA_CCR_WEX | STM32_MDMA_CCR_HEX | in stm32_mdma_set_xfer_param()
537 ccr |= STM32_MDMA_CCR_PL(chan_config->priority_level); in stm32_mdma_set_xfer_param()
666 *mdma_ccr = ccr; in stm32_mdma_set_xfer_param()
735 u32 m2m_hw_period, ccr, ctcr, ctbr; in stm32_mdma_setup_xfer() local
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-mpc512x-psc.c90 u32 ccr; in mpc512x_psc_spi_activate_cs() local
113 ccr = in_be32(psc_addr(mps, ccr)); in mpc512x_psc_spi_activate_cs()
114 ccr &= 0xFF000000; in mpc512x_psc_spi_activate_cs()
120 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); in mpc512x_psc_spi_activate_cs()
121 out_be32(psc_addr(mps, ccr), ccr); in mpc512x_psc_spi_activate_cs()
388 u32 ccr; in mpc512x_psc_spi_port_config() local
416 ccr = in_be32(psc_addr(mps, ccr)); in mpc512x_psc_spi_port_config()
417 ccr &= 0xFF000000; in mpc512x_psc_spi_port_config()
420 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); in mpc512x_psc_spi_port_config()
421 out_be32(psc_addr(mps, ccr), ccr); in mpc512x_psc_spi_port_config()
H A Dspi-mpc52xx-psc.c66 u16 ccr; in mpc52xx_psc_spi_activate_cs() local
90 ccr = in_be16((u16 __iomem *)&psc->ccr); in mpc52xx_psc_spi_activate_cs()
91 ccr &= 0xFF00; in mpc52xx_psc_spi_activate_cs()
93 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
95 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
96 out_be16((u16 __iomem *)&psc->ccr, ccr); in mpc52xx_psc_spi_activate_cs()
269 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ in mpc52xx_psc_spi_port_config()
/openbmc/linux/drivers/rtc/
H A Drtc-isl12026.c206 u8 ccr[8]; in isl12026_rtc_read_time() local
243 msgs[1].len = sizeof(ccr); in isl12026_rtc_read_time()
244 msgs[1].buf = ccr; in isl12026_rtc_read_time()
253 tm->tm_sec = bcd2bin(ccr[0] & 0x7F); in isl12026_rtc_read_time()
254 tm->tm_min = bcd2bin(ccr[1] & 0x7F); in isl12026_rtc_read_time()
255 if (ccr[2] & ISL12026_REG_HR_MIL) in isl12026_rtc_read_time()
256 tm->tm_hour = bcd2bin(ccr[2] & 0x3F); in isl12026_rtc_read_time()
258 tm->tm_hour = bcd2bin(ccr[2] & 0x1F) + in isl12026_rtc_read_time()
259 ((ccr[2] & 0x20) ? 12 : 0); in isl12026_rtc_read_time()
260 tm->tm_mday = bcd2bin(ccr[3] & 0x3F); in isl12026_rtc_read_time()
[all …]
H A Drtc-xgene.c79 u32 ccr; in xgene_rtc_alarm_irq_enable() local
81 ccr = readl(pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
83 ccr &= ~RTC_CCR_MASK; in xgene_rtc_alarm_irq_enable()
84 ccr |= RTC_CCR_IE; in xgene_rtc_alarm_irq_enable()
86 ccr &= ~RTC_CCR_IE; in xgene_rtc_alarm_irq_enable()
87 ccr |= RTC_CCR_MASK; in xgene_rtc_alarm_irq_enable()
89 writel(ccr, pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
/openbmc/linux/drivers/dma/ti/
H A Domap-dma.c67 uint32_t ccr; member
121 uint32_t ccr; /* CCR value */ member
457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
508 if (!(c->ccr & CCR_BUFFERING_DISABLE)) in omap_dma_stop()
519 if (!(c->ccr & CCR_BUFFERING_DISABLE)) in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
589 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
744 c->ccr = CCR_OMAP31_DISABLE; in omap_dma_alloc_chan_resources()
746 c->ccr |= c->dma_ch + 1; in omap_dma_alloc_chan_resources()
748 c->ccr = c->dma_sig & 0x1f; in omap_dma_alloc_chan_resources()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c210 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE)); in dcache_enable()
228 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE)); in dcache_disable()
237 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0; in dcache_status()
312 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_enable()
321 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0; in icache_status()
330 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_disable()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c115 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
122 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
391 setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); in dramc_scan_readpipe()
394 await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING); in dramc_scan_readpipe()
503 setbits_le32(&dram->ccr, DRAM_CCR_INIT); in mctl_ddr3_initialize()
504 await_bits_clear(&dram->ccr, DRAM_CCR_INIT); in mctl_ddr3_initialize()
630 await_bits_clear(&dram->ccr, DRAM_CCR_INIT); in dramc_init_helper()
655 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); in dramc_init_helper()
660 setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); in dramc_init_helper()
680 clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); in dramc_init_helper()
[all …]
/openbmc/qemu/target/sparc/
H A Dwin_helper.c270 target_ulong ccr = 0; in cpu_get_ccr() local
272 ccr |= (env->icc_C >> 32) & 1; in cpu_get_ccr()
273 ccr |= ((int32_t)env->cc_V < 0) << 1; in cpu_get_ccr()
274 ccr |= ((int32_t)env->icc_Z == 0) << 2; in cpu_get_ccr()
275 ccr |= ((int32_t)env->cc_N < 0) << 3; in cpu_get_ccr()
277 ccr |= env->xcc_C << 4; in cpu_get_ccr()
278 ccr |= (env->cc_V < 0) << 5; in cpu_get_ccr()
279 ccr |= (env->xcc_Z == 0) << 6; in cpu_get_ccr()
280 ccr |= (env->cc_N < 0) << 7; in cpu_get_ccr()
282 return ccr; in cpu_get_ccr()
/openbmc/linux/arch/sh/kernel/cpu/
H A Dinit.c109 unsigned long ccr, flags; in cache_init() local
112 ccr = __raw_readl(SH_CCR); in cache_init()
125 if (ccr & CCR_CACHE_ENABLE) { in cache_init()
135 if (ccr & CCR_CACHE_ORA) in cache_init()
143 if (!(ccr & CCR_CACHE_EMODE)) in cache_init()
/openbmc/linux/arch/sparc/include/asm/
H A Dbackoff.h57 88: rd %ccr, %g0; \
58 rd %ccr, %g0; \
59 rd %ccr, %g0; \
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv_tm_builtin.c101 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | in kvmhv_p9_tm_emulation_early()
118 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000; in kvmhv_emulate_tm_rollback()
H A Dbook3s_hv_tm.c156 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | in kvmhv_p9_tm_emulation()
203 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | in kvmhv_p9_tm_emulation()
236 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | in kvmhv_p9_tm_emulation()
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c76 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
148 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || in setup_5445x_clocks()
149 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { in setup_5445x_clocks()
170 fbtemp = pPllmult[ccm->ccr & fbpll_mask]; in setup_5445x_clocks()
228 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; in setup_5445x_clocks()
239 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in setup_5445x_clocks()
/openbmc/u-boot/arch/sh/cpu/sh4/
H A Dcache.c39 unsigned long ccr; in cache_control() local
42 ccr = inl(CCR); in cache_control()
44 if (ccr & CCR_CACHE_ENABLE) in cache_control()

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