12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon * Overview:
493db446aSBoris Brezillon * Platform independent driver for NDFC (NanD Flash Controller)
593db446aSBoris Brezillon * integrated into EP440 cores
693db446aSBoris Brezillon *
793db446aSBoris Brezillon * Ported to an OF platform driver by Sean MacLennan
893db446aSBoris Brezillon *
993db446aSBoris Brezillon * The NDFC supports multiple chips, but this driver only supports a
1093db446aSBoris Brezillon * single chip since I do not have access to any boards with
1193db446aSBoris Brezillon * multiple chips.
1293db446aSBoris Brezillon *
1393db446aSBoris Brezillon * Author: Thomas Gleixner
1493db446aSBoris Brezillon *
1593db446aSBoris Brezillon * Copyright 2006 IBM
1693db446aSBoris Brezillon * Copyright 2008 PIKA Technologies
1793db446aSBoris Brezillon * Sean MacLennan <smaclennan@pikatech.com>
1893db446aSBoris Brezillon */
1993db446aSBoris Brezillon #include <linux/module.h>
2093db446aSBoris Brezillon #include <linux/mtd/rawnand.h>
2193db446aSBoris Brezillon #include <linux/mtd/partitions.h>
2293db446aSBoris Brezillon #include <linux/mtd/ndfc.h>
2393db446aSBoris Brezillon #include <linux/slab.h>
2493db446aSBoris Brezillon #include <linux/mtd/mtd.h>
25*c2fc6b69SRob Herring #include <linux/of.h>
2693db446aSBoris Brezillon #include <linux/of_address.h>
27*c2fc6b69SRob Herring #include <linux/platform_device.h>
2893db446aSBoris Brezillon #include <asm/io.h>
2993db446aSBoris Brezillon
3093db446aSBoris Brezillon #define NDFC_MAX_CS 4
3193db446aSBoris Brezillon
3293db446aSBoris Brezillon struct ndfc_controller {
3393db446aSBoris Brezillon struct platform_device *ofdev;
3493db446aSBoris Brezillon void __iomem *ndfcbase;
3593db446aSBoris Brezillon struct nand_chip chip;
3693db446aSBoris Brezillon int chip_select;
377da45139SMiquel Raynal struct nand_controller ndfc_control;
3893db446aSBoris Brezillon };
3993db446aSBoris Brezillon
4093db446aSBoris Brezillon static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
4193db446aSBoris Brezillon
ndfc_select_chip(struct nand_chip * nchip,int chip)42758b56f5SBoris Brezillon static void ndfc_select_chip(struct nand_chip *nchip, int chip)
4393db446aSBoris Brezillon {
4493db446aSBoris Brezillon uint32_t ccr;
4593db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(nchip);
4693db446aSBoris Brezillon
4793db446aSBoris Brezillon ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
4893db446aSBoris Brezillon if (chip >= 0) {
4993db446aSBoris Brezillon ccr &= ~NDFC_CCR_BS_MASK;
5093db446aSBoris Brezillon ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
5193db446aSBoris Brezillon } else
5293db446aSBoris Brezillon ccr |= NDFC_CCR_RESET_CE;
5393db446aSBoris Brezillon out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
5493db446aSBoris Brezillon }
5593db446aSBoris Brezillon
ndfc_hwcontrol(struct nand_chip * chip,int cmd,unsigned int ctrl)560f808c16SBoris Brezillon static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
5793db446aSBoris Brezillon {
5893db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
5993db446aSBoris Brezillon
6093db446aSBoris Brezillon if (cmd == NAND_CMD_NONE)
6193db446aSBoris Brezillon return;
6293db446aSBoris Brezillon
6393db446aSBoris Brezillon if (ctrl & NAND_CLE)
6493db446aSBoris Brezillon writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
6593db446aSBoris Brezillon else
6693db446aSBoris Brezillon writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
6793db446aSBoris Brezillon }
6893db446aSBoris Brezillon
ndfc_ready(struct nand_chip * chip)6950a487e7SBoris Brezillon static int ndfc_ready(struct nand_chip *chip)
7093db446aSBoris Brezillon {
7193db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
7293db446aSBoris Brezillon
7393db446aSBoris Brezillon return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
7493db446aSBoris Brezillon }
7593db446aSBoris Brezillon
ndfc_enable_hwecc(struct nand_chip * chip,int mode)76ec47636cSBoris Brezillon static void ndfc_enable_hwecc(struct nand_chip *chip, int mode)
7793db446aSBoris Brezillon {
7893db446aSBoris Brezillon uint32_t ccr;
7993db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
8093db446aSBoris Brezillon
8193db446aSBoris Brezillon ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
8293db446aSBoris Brezillon ccr |= NDFC_CCR_RESET_ECC;
8393db446aSBoris Brezillon out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
8493db446aSBoris Brezillon wmb();
8593db446aSBoris Brezillon }
8693db446aSBoris Brezillon
ndfc_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)87af37d2c3SBoris Brezillon static int ndfc_calculate_ecc(struct nand_chip *chip,
8893db446aSBoris Brezillon const u_char *dat, u_char *ecc_code)
8993db446aSBoris Brezillon {
9093db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
9193db446aSBoris Brezillon uint32_t ecc;
9293db446aSBoris Brezillon uint8_t *p = (uint8_t *)&ecc;
9393db446aSBoris Brezillon
9493db446aSBoris Brezillon wmb();
9593db446aSBoris Brezillon ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
9693db446aSBoris Brezillon /* The NDFC uses Smart Media (SMC) bytes order */
9793db446aSBoris Brezillon ecc_code[0] = p[1];
9893db446aSBoris Brezillon ecc_code[1] = p[2];
9993db446aSBoris Brezillon ecc_code[2] = p[3];
10093db446aSBoris Brezillon
10193db446aSBoris Brezillon return 0;
10293db446aSBoris Brezillon }
10393db446aSBoris Brezillon
10493db446aSBoris Brezillon /*
10593db446aSBoris Brezillon * Speedups for buffer read/write/verify
10693db446aSBoris Brezillon *
10793db446aSBoris Brezillon * NDFC allows 32bit read/write of data. So we can speed up the buffer
10893db446aSBoris Brezillon * functions. No further checking, as nand_base will always read/write
10993db446aSBoris Brezillon * page aligned.
11093db446aSBoris Brezillon */
ndfc_read_buf(struct nand_chip * chip,uint8_t * buf,int len)1117e534323SBoris Brezillon static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
11293db446aSBoris Brezillon {
11393db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
11493db446aSBoris Brezillon uint32_t *p = (uint32_t *) buf;
11593db446aSBoris Brezillon
11693db446aSBoris Brezillon for(;len > 0; len -= 4)
11793db446aSBoris Brezillon *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
11893db446aSBoris Brezillon }
11993db446aSBoris Brezillon
ndfc_write_buf(struct nand_chip * chip,const uint8_t * buf,int len)120c0739d85SBoris Brezillon static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
12193db446aSBoris Brezillon {
12293db446aSBoris Brezillon struct ndfc_controller *ndfc = nand_get_controller_data(chip);
12393db446aSBoris Brezillon uint32_t *p = (uint32_t *) buf;
12493db446aSBoris Brezillon
12593db446aSBoris Brezillon for(;len > 0; len -= 4)
12693db446aSBoris Brezillon out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
12793db446aSBoris Brezillon }
12893db446aSBoris Brezillon
12993db446aSBoris Brezillon /*
13093db446aSBoris Brezillon * Initialize chip structure
13193db446aSBoris Brezillon */
ndfc_chip_init(struct ndfc_controller * ndfc,struct device_node * node)13293db446aSBoris Brezillon static int ndfc_chip_init(struct ndfc_controller *ndfc,
13393db446aSBoris Brezillon struct device_node *node)
13493db446aSBoris Brezillon {
13593db446aSBoris Brezillon struct device_node *flash_np;
13693db446aSBoris Brezillon struct nand_chip *chip = &ndfc->chip;
13793db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
13893db446aSBoris Brezillon int ret;
13993db446aSBoris Brezillon
14082fc5099SBoris Brezillon chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
14182fc5099SBoris Brezillon chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
142bf6065c6SBoris Brezillon chip->legacy.cmd_ctrl = ndfc_hwcontrol;
1438395b753SBoris Brezillon chip->legacy.dev_ready = ndfc_ready;
1447d6c37e9SBoris Brezillon chip->legacy.select_chip = ndfc_select_chip;
1453cece3abSBoris Brezillon chip->legacy.chip_delay = 50;
14693db446aSBoris Brezillon chip->controller = &ndfc->ndfc_control;
147716bbbabSBoris Brezillon chip->legacy.read_buf = ndfc_read_buf;
148716bbbabSBoris Brezillon chip->legacy.write_buf = ndfc_write_buf;
1498d1e4218SMiquel Raynal chip->ecc.correct = rawnand_sw_hamming_correct;
15093db446aSBoris Brezillon chip->ecc.hwctl = ndfc_enable_hwecc;
15193db446aSBoris Brezillon chip->ecc.calculate = ndfc_calculate_ecc;
152bace41f8SMiquel Raynal chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
15393db446aSBoris Brezillon chip->ecc.size = 256;
15493db446aSBoris Brezillon chip->ecc.bytes = 3;
15593db446aSBoris Brezillon chip->ecc.strength = 1;
15693db446aSBoris Brezillon nand_set_controller_data(chip, ndfc);
15793db446aSBoris Brezillon
15893db446aSBoris Brezillon mtd->dev.parent = &ndfc->ofdev->dev;
15993db446aSBoris Brezillon
16093db446aSBoris Brezillon flash_np = of_get_next_child(node, NULL);
16193db446aSBoris Brezillon if (!flash_np)
16293db446aSBoris Brezillon return -ENODEV;
16393db446aSBoris Brezillon nand_set_flash_node(chip, flash_np);
16493db446aSBoris Brezillon
165a9fdba0bSRob Herring mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev),
166a9fdba0bSRob Herring flash_np);
16793db446aSBoris Brezillon if (!mtd->name) {
16893db446aSBoris Brezillon ret = -ENOMEM;
16993db446aSBoris Brezillon goto err;
17093db446aSBoris Brezillon }
17193db446aSBoris Brezillon
17200ad378fSBoris Brezillon ret = nand_scan(chip, 1);
17393db446aSBoris Brezillon if (ret)
17493db446aSBoris Brezillon goto err;
17593db446aSBoris Brezillon
17693db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0);
17793db446aSBoris Brezillon
17893db446aSBoris Brezillon err:
17993db446aSBoris Brezillon of_node_put(flash_np);
18093db446aSBoris Brezillon if (ret)
18193db446aSBoris Brezillon kfree(mtd->name);
18293db446aSBoris Brezillon return ret;
18393db446aSBoris Brezillon }
18493db446aSBoris Brezillon
ndfc_probe(struct platform_device * ofdev)18593db446aSBoris Brezillon static int ndfc_probe(struct platform_device *ofdev)
18693db446aSBoris Brezillon {
18793db446aSBoris Brezillon struct ndfc_controller *ndfc;
18893db446aSBoris Brezillon const __be32 *reg;
18993db446aSBoris Brezillon u32 ccr;
19093db446aSBoris Brezillon u32 cs;
19193db446aSBoris Brezillon int err, len;
19293db446aSBoris Brezillon
19393db446aSBoris Brezillon /* Read the reg property to get the chip select */
19493db446aSBoris Brezillon reg = of_get_property(ofdev->dev.of_node, "reg", &len);
19593db446aSBoris Brezillon if (reg == NULL || len != 12) {
19693db446aSBoris Brezillon dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
19793db446aSBoris Brezillon return -ENOENT;
19893db446aSBoris Brezillon }
19993db446aSBoris Brezillon
20093db446aSBoris Brezillon cs = be32_to_cpu(reg[0]);
20193db446aSBoris Brezillon if (cs >= NDFC_MAX_CS) {
20293db446aSBoris Brezillon dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
20393db446aSBoris Brezillon return -EINVAL;
20493db446aSBoris Brezillon }
20593db446aSBoris Brezillon
20693db446aSBoris Brezillon ndfc = &ndfc_ctrl[cs];
20793db446aSBoris Brezillon ndfc->chip_select = cs;
20893db446aSBoris Brezillon
2097da45139SMiquel Raynal nand_controller_init(&ndfc->ndfc_control);
21093db446aSBoris Brezillon ndfc->ofdev = ofdev;
21193db446aSBoris Brezillon dev_set_drvdata(&ofdev->dev, ndfc);
21293db446aSBoris Brezillon
21393db446aSBoris Brezillon ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
21493db446aSBoris Brezillon if (!ndfc->ndfcbase) {
21593db446aSBoris Brezillon dev_err(&ofdev->dev, "failed to get memory\n");
21693db446aSBoris Brezillon return -EIO;
21793db446aSBoris Brezillon }
21893db446aSBoris Brezillon
21993db446aSBoris Brezillon ccr = NDFC_CCR_BS(ndfc->chip_select);
22093db446aSBoris Brezillon
22193db446aSBoris Brezillon /* It is ok if ccr does not exist - just default to 0 */
22293db446aSBoris Brezillon reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
22393db446aSBoris Brezillon if (reg)
22493db446aSBoris Brezillon ccr |= be32_to_cpup(reg);
22593db446aSBoris Brezillon
22693db446aSBoris Brezillon out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
22793db446aSBoris Brezillon
22893db446aSBoris Brezillon /* Set the bank settings if given */
22993db446aSBoris Brezillon reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
23093db446aSBoris Brezillon if (reg) {
23193db446aSBoris Brezillon int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
23293db446aSBoris Brezillon out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
23393db446aSBoris Brezillon }
23493db446aSBoris Brezillon
23593db446aSBoris Brezillon err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
23693db446aSBoris Brezillon if (err) {
23793db446aSBoris Brezillon iounmap(ndfc->ndfcbase);
23893db446aSBoris Brezillon return err;
23993db446aSBoris Brezillon }
24093db446aSBoris Brezillon
24193db446aSBoris Brezillon return 0;
24293db446aSBoris Brezillon }
24393db446aSBoris Brezillon
ndfc_remove(struct platform_device * ofdev)244ec185b18SUwe Kleine-König static void ndfc_remove(struct platform_device *ofdev)
24593db446aSBoris Brezillon {
24693db446aSBoris Brezillon struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
247a9384f95SMiquel Raynal struct nand_chip *chip = &ndfc->chip;
248a9384f95SMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip);
249a9384f95SMiquel Raynal int ret;
25093db446aSBoris Brezillon
251a9384f95SMiquel Raynal ret = mtd_device_unregister(mtd);
252a9384f95SMiquel Raynal WARN_ON(ret);
253a9384f95SMiquel Raynal nand_cleanup(chip);
25493db446aSBoris Brezillon kfree(mtd->name);
25593db446aSBoris Brezillon }
25693db446aSBoris Brezillon
25793db446aSBoris Brezillon static const struct of_device_id ndfc_match[] = {
25893db446aSBoris Brezillon { .compatible = "ibm,ndfc", },
25993db446aSBoris Brezillon {}
26093db446aSBoris Brezillon };
26193db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, ndfc_match);
26293db446aSBoris Brezillon
26393db446aSBoris Brezillon static struct platform_driver ndfc_driver = {
26493db446aSBoris Brezillon .driver = {
26593db446aSBoris Brezillon .name = "ndfc",
26693db446aSBoris Brezillon .of_match_table = ndfc_match,
26793db446aSBoris Brezillon },
26893db446aSBoris Brezillon .probe = ndfc_probe,
269ec185b18SUwe Kleine-König .remove_new = ndfc_remove,
27093db446aSBoris Brezillon };
27193db446aSBoris Brezillon
27293db446aSBoris Brezillon module_platform_driver(ndfc_driver);
27393db446aSBoris Brezillon
27493db446aSBoris Brezillon MODULE_LICENSE("GPL");
27593db446aSBoris Brezillon MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
27693db446aSBoris Brezillon MODULE_DESCRIPTION("OF Platform driver for NDFC");
277