Searched refs:cbar (Results 1 – 6 of 6) sorted by relevance
155 unsigned int cbar; /* 0xffc */ member
2164 u32 cbar, crat, vstat; in tsi148_crcsr_init() local2186 cbar = ioread32be(bridge->base + TSI148_CBAR); in tsi148_crcsr_init()2187 cbar = (cbar & TSI148_CRCSR_CBAR_M) >> 3; in tsi148_crcsr_init()2191 if (cbar != vstat) { in tsi148_crcsr_init()2192 cbar = vstat; in tsi148_crcsr_init()2194 iowrite32be(cbar << 3, bridge->base + TSI148_CBAR); in tsi148_crcsr_init()2196 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); in tsi148_crcsr_init()
459 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank()524 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_write_context_bank()540 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, cfg->cbar); in arm_smmu_write_context_bank()684 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()707 cfg->cbar = CBAR_TYPE_S2_TRANS; in arm_smmu_init_domain_context()
347 enum arm_smmu_cbar_type cbar; member
104 u32 cbar; member
9804 ARMCPRegInfo cbar = { in register_cp_regs_for_features() local9812 cbar.access = PL1_R; in register_cp_regs_for_features()9813 cbar.fieldoffset = 0; in register_cp_regs_for_features()9814 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features()9816 define_one_arm_cp_reg(cpu, &cbar); in register_cp_regs_for_features()