1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 252a0e2deSReinhard Arlt /* 352a0e2deSReinhard Arlt * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com 452a0e2deSReinhard Arlt * 552a0e2deSReinhard Arlt * base on universe.h by 652a0e2deSReinhard Arlt * 752a0e2deSReinhard Arlt * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com 852a0e2deSReinhard Arlt */ 952a0e2deSReinhard Arlt 1052a0e2deSReinhard Arlt #ifndef _tsi148_h 1152a0e2deSReinhard Arlt #define _tsi148_h 1252a0e2deSReinhard Arlt 1352a0e2deSReinhard Arlt #ifndef PCI_DEVICE_ID_TUNDRA_TSI148 1452a0e2deSReinhard Arlt #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148 1552a0e2deSReinhard Arlt #endif 1652a0e2deSReinhard Arlt 1752a0e2deSReinhard Arlt typedef struct _TSI148 TSI148; 1852a0e2deSReinhard Arlt typedef struct _OUTBOUND OUTBOUND; 1952a0e2deSReinhard Arlt typedef struct _INBOUND INBOUND; 2052a0e2deSReinhard Arlt typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; 2152a0e2deSReinhard Arlt 2252a0e2deSReinhard Arlt struct _OUTBOUND { 2352a0e2deSReinhard Arlt unsigned int otsau; /* 0x000 Outbound start upper */ 2452a0e2deSReinhard Arlt unsigned int otsal; /* 0x004 Outbouud start lower */ 2552a0e2deSReinhard Arlt unsigned int oteau; /* 0x008 Outbound end upper */ 2652a0e2deSReinhard Arlt unsigned int oteal; /* 0x00c Outbound end lower */ 2752a0e2deSReinhard Arlt unsigned int otofu; /* 0x010 Outbound translation upper */ 2852a0e2deSReinhard Arlt unsigned int otofl; /* 0x014 Outbound translation lower */ 2952a0e2deSReinhard Arlt unsigned int otbs; /* 0x018 Outbound translation 2eSST */ 3052a0e2deSReinhard Arlt unsigned int otat; /* 0x01c Outbound translation attr */ 3152a0e2deSReinhard Arlt }; 3252a0e2deSReinhard Arlt 3352a0e2deSReinhard Arlt struct _INBOUND { 3452a0e2deSReinhard Arlt unsigned int itsau; /* 0x000 inbound start upper */ 3552a0e2deSReinhard Arlt unsigned int itsal; /* 0x004 inbouud start lower */ 3652a0e2deSReinhard Arlt unsigned int iteau; /* 0x008 inbound end upper */ 3752a0e2deSReinhard Arlt unsigned int iteal; /* 0x00c inbound end lower */ 3852a0e2deSReinhard Arlt unsigned int itofu; /* 0x010 inbound translation upper */ 3952a0e2deSReinhard Arlt unsigned int itofl; /* 0x014 inbound translation lower */ 4052a0e2deSReinhard Arlt unsigned int itat; /* 0x018 inbound translation attr */ 4152a0e2deSReinhard Arlt unsigned int spare; /* 0x01c not used */ 4252a0e2deSReinhard Arlt }; 4352a0e2deSReinhard Arlt 4452a0e2deSReinhard Arlt struct _TSI148 { 4552a0e2deSReinhard Arlt unsigned int pci_id; /* 0x000 */ 4652a0e2deSReinhard Arlt unsigned int pci_csr; /* 0x004 */ 4752a0e2deSReinhard Arlt unsigned int pci_class; /* 0x008 */ 4852a0e2deSReinhard Arlt unsigned int pci_misc0; /* 0x00c */ 4952a0e2deSReinhard Arlt unsigned int pci_mbarl; /* 0x010 */ 5052a0e2deSReinhard Arlt unsigned int pci_mbarh; /* 0x014 */ 5152a0e2deSReinhard Arlt unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */ 5252a0e2deSReinhard Arlt unsigned int pci_misc1; /* 0x03c */ 5352a0e2deSReinhard Arlt unsigned int pci_pcixcap; /* 0x040 */ 5452a0e2deSReinhard Arlt unsigned int pci_pcixstat; /* 0x044 */ 5552a0e2deSReinhard Arlt unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */ 5652a0e2deSReinhard Arlt OUTBOUND outbound[8]; /* 0x100 */ 5752a0e2deSReinhard Arlt unsigned int viack[8]; /* 0x204 */ 5852a0e2deSReinhard Arlt unsigned int rmwau; /* 0x220 */ 5952a0e2deSReinhard Arlt unsigned int rmwal; /* 0x224 */ 6052a0e2deSReinhard Arlt unsigned int rmwen; /* 0x228 */ 6152a0e2deSReinhard Arlt unsigned int rmwc; /* 0x22c */ 6252a0e2deSReinhard Arlt unsigned int rmws; /* 0x230 */ 6352a0e2deSReinhard Arlt unsigned int vmctrl; /* 0x234 */ 6452a0e2deSReinhard Arlt unsigned int vctrl; /* 0x238 */ 6552a0e2deSReinhard Arlt unsigned int vstat; /* 0x23c */ 6652a0e2deSReinhard Arlt unsigned int pcsr; /* 0x240 */ 6752a0e2deSReinhard Arlt unsigned int spare2[3]; /* 0x244 - 0x24c */ 6852a0e2deSReinhard Arlt unsigned int vmefl; /* 0x250 */ 6952a0e2deSReinhard Arlt unsigned int spare3[3]; /* 0x254 - 0x25c */ 7052a0e2deSReinhard Arlt unsigned int veau; /* 0x260 */ 7152a0e2deSReinhard Arlt unsigned int veal; /* 0x264 */ 7252a0e2deSReinhard Arlt unsigned int veat; /* 0x268 */ 7352a0e2deSReinhard Arlt unsigned int spare4[1]; /* 0x26c */ 7452a0e2deSReinhard Arlt unsigned int edpau; /* 0x270 */ 7552a0e2deSReinhard Arlt unsigned int edpal; /* 0x274 */ 7652a0e2deSReinhard Arlt unsigned int edpxa; /* 0x278 */ 7752a0e2deSReinhard Arlt unsigned int edpxs; /* 0x27c */ 7852a0e2deSReinhard Arlt unsigned int edpat; /* 0x280 */ 7952a0e2deSReinhard Arlt unsigned int spare5[31]; /* 0x284 - 0x2fc */ 8052a0e2deSReinhard Arlt INBOUND inbound[8]; /* 0x100 */ 8152a0e2deSReinhard Arlt unsigned int gbau; /* 0x400 */ 8252a0e2deSReinhard Arlt unsigned int gbal; /* 0x404 */ 8352a0e2deSReinhard Arlt unsigned int gcsrat; /* 0x408 */ 8452a0e2deSReinhard Arlt unsigned int cbau; /* 0x40c */ 8552a0e2deSReinhard Arlt unsigned int cbal; /* 0x410 */ 8652a0e2deSReinhard Arlt unsigned int crgat; /* 0x414 */ 8752a0e2deSReinhard Arlt unsigned int crou; /* 0x418 */ 8852a0e2deSReinhard Arlt unsigned int crol; /* 0x41c */ 8952a0e2deSReinhard Arlt unsigned int crat; /* 0x420 */ 9052a0e2deSReinhard Arlt unsigned int lmbau; /* 0x424 */ 9152a0e2deSReinhard Arlt unsigned int lmbal; /* 0x428 */ 9252a0e2deSReinhard Arlt unsigned int lmat; /* 0x42c */ 9352a0e2deSReinhard Arlt unsigned int r64bcu; /* 0x430 */ 9452a0e2deSReinhard Arlt unsigned int r64bcl; /* 0x434 */ 9552a0e2deSReinhard Arlt unsigned int bpgtr; /* 0x438 */ 9652a0e2deSReinhard Arlt unsigned int bpctr; /* 0x43c */ 9752a0e2deSReinhard Arlt unsigned int vicr; /* 0x440 */ 9852a0e2deSReinhard Arlt unsigned int spare6[1]; /* 0x444 */ 9952a0e2deSReinhard Arlt unsigned int inten; /* 0x448 */ 10052a0e2deSReinhard Arlt unsigned int inteo; /* 0x44c */ 10152a0e2deSReinhard Arlt unsigned int ints; /* 0x450 */ 10252a0e2deSReinhard Arlt unsigned int intc; /* 0x454 */ 10352a0e2deSReinhard Arlt unsigned int intm1; /* 0x458 */ 10452a0e2deSReinhard Arlt unsigned int intm2; /* 0x45c */ 10552a0e2deSReinhard Arlt unsigned int spare7[40]; /* 0x460 - 0x4fc */ 10652a0e2deSReinhard Arlt unsigned int dctl0; /* 0x500 */ 10752a0e2deSReinhard Arlt unsigned int dsta0; /* 0x504 */ 10852a0e2deSReinhard Arlt unsigned int dcsau0; /* 0x508 */ 10952a0e2deSReinhard Arlt unsigned int dcsal0; /* 0x50c */ 11052a0e2deSReinhard Arlt unsigned int dcdau0; /* 0x510 */ 11152a0e2deSReinhard Arlt unsigned int dcdal0; /* 0x514 */ 11252a0e2deSReinhard Arlt unsigned int dclau0; /* 0x518 */ 11352a0e2deSReinhard Arlt unsigned int dclal0; /* 0x51c */ 11452a0e2deSReinhard Arlt unsigned int dsau0; /* 0x520 */ 11552a0e2deSReinhard Arlt unsigned int dsal0; /* 0x524 */ 11652a0e2deSReinhard Arlt unsigned int ddau0; /* 0x528 */ 11752a0e2deSReinhard Arlt unsigned int ddal0; /* 0x52c */ 11852a0e2deSReinhard Arlt unsigned int dsat0; /* 0x530 */ 11952a0e2deSReinhard Arlt unsigned int ddat0; /* 0x534 */ 12052a0e2deSReinhard Arlt unsigned int dnlau0; /* 0x538 */ 12152a0e2deSReinhard Arlt unsigned int dnlal0; /* 0x53c */ 12252a0e2deSReinhard Arlt unsigned int dcnt0; /* 0x540 */ 12352a0e2deSReinhard Arlt unsigned int ddbs0; /* 0x544 */ 12452a0e2deSReinhard Arlt unsigned int r20[14]; /* 0x548 - 0x57c */ 12552a0e2deSReinhard Arlt unsigned int dctl1; /* 0x580 */ 12652a0e2deSReinhard Arlt unsigned int dsta1; /* 0x584 */ 12752a0e2deSReinhard Arlt unsigned int dcsau1; /* 0x588 */ 12852a0e2deSReinhard Arlt unsigned int dcsal1; /* 0x58c */ 12952a0e2deSReinhard Arlt unsigned int dcdau1; /* 0x590 */ 13052a0e2deSReinhard Arlt unsigned int dcdal1; /* 0x594 */ 13152a0e2deSReinhard Arlt unsigned int dclau1; /* 0x598 */ 13252a0e2deSReinhard Arlt unsigned int dclal1; /* 0x59c */ 13352a0e2deSReinhard Arlt unsigned int dsau1; /* 0x5a0 */ 13452a0e2deSReinhard Arlt unsigned int dsal1; /* 0x5a4 */ 13552a0e2deSReinhard Arlt unsigned int ddau1; /* 0x5a8 */ 13652a0e2deSReinhard Arlt unsigned int ddal1; /* 0x5ac */ 13752a0e2deSReinhard Arlt unsigned int dsat1; /* 0x5b0 */ 13852a0e2deSReinhard Arlt unsigned int ddat1; /* 0x5b4 */ 13952a0e2deSReinhard Arlt unsigned int dnlau1; /* 0x5b8 */ 14052a0e2deSReinhard Arlt unsigned int dnlal1; /* 0x5bc */ 14152a0e2deSReinhard Arlt unsigned int dcnt1; /* 0x5c0 */ 14252a0e2deSReinhard Arlt unsigned int ddbs1; /* 0x5c4 */ 14352a0e2deSReinhard Arlt unsigned int r21[14]; /* 0x5c8 - 0x5fc */ 14452a0e2deSReinhard Arlt unsigned int devi_veni_2; /* 0x600 */ 14552a0e2deSReinhard Arlt unsigned int gctrl_ga_revid; /* 0x604 */ 14652a0e2deSReinhard Arlt unsigned int semaphore0_1_2_3; /* 0x608 */ 14752a0e2deSReinhard Arlt unsigned int semaphore4_5_6_7; /* 0x60c */ 14852a0e2deSReinhard Arlt unsigned int mbox0; /* 0x610 */ 14952a0e2deSReinhard Arlt unsigned int mbox1; /* 0x614 */ 15052a0e2deSReinhard Arlt unsigned int mbox2; /* 0x618 */ 15152a0e2deSReinhard Arlt unsigned int mbox3; /* 0x61c */ 15252a0e2deSReinhard Arlt unsigned int r22[629]; /* 0x620 - 0xff0 */ 15352a0e2deSReinhard Arlt unsigned int csrbcr; /* 0xff4 */ 15452a0e2deSReinhard Arlt unsigned int csrbsr; /* 0xff8 */ 15552a0e2deSReinhard Arlt unsigned int cbar; /* 0xffc */ 15652a0e2deSReinhard Arlt }; 15752a0e2deSReinhard Arlt 15852a0e2deSReinhard Arlt #define IRQ_VOWN 0x0001 15952a0e2deSReinhard Arlt #define IRQ_VIRQ1 0x0002 16052a0e2deSReinhard Arlt #define IRQ_VIRQ2 0x0004 16152a0e2deSReinhard Arlt #define IRQ_VIRQ3 0x0008 16252a0e2deSReinhard Arlt #define IRQ_VIRQ4 0x0010 16352a0e2deSReinhard Arlt #define IRQ_VIRQ5 0x0020 16452a0e2deSReinhard Arlt #define IRQ_VIRQ6 0x0040 16552a0e2deSReinhard Arlt #define IRQ_VIRQ7 0x0080 16652a0e2deSReinhard Arlt #define IRQ_DMA 0x0100 16752a0e2deSReinhard Arlt #define IRQ_LERR 0x0200 16852a0e2deSReinhard Arlt #define IRQ_VERR 0x0400 16952a0e2deSReinhard Arlt #define IRQ_res 0x0800 17052a0e2deSReinhard Arlt #define IRQ_IACK 0x1000 17152a0e2deSReinhard Arlt #define IRQ_SWINT 0x2000 17252a0e2deSReinhard Arlt #define IRQ_SYSFAIL 0x4000 17352a0e2deSReinhard Arlt #define IRQ_ACFAIL 0x8000 17452a0e2deSReinhard Arlt 17552a0e2deSReinhard Arlt struct _TDMA_CMD_PACKET { 17652a0e2deSReinhard Arlt unsigned int dctl; /* DMA Control */ 17752a0e2deSReinhard Arlt unsigned int dtbc; /* Transfer Byte Count */ 17852a0e2deSReinhard Arlt unsigned int dlv; /* PCI Address */ 17952a0e2deSReinhard Arlt unsigned int res1; /* Reserved */ 18052a0e2deSReinhard Arlt unsigned int dva; /* Vme Address */ 18152a0e2deSReinhard Arlt unsigned int res2; /* Reserved */ 18252a0e2deSReinhard Arlt unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 18352a0e2deSReinhard Arlt unsigned int res3; /* Reserved */ 18452a0e2deSReinhard Arlt }; 18552a0e2deSReinhard Arlt 18652a0e2deSReinhard Arlt #define VME_AM_A16 0x01 18752a0e2deSReinhard Arlt #define VME_AM_A24 0x02 18852a0e2deSReinhard Arlt #define VME_AM_A32 0x03 18952a0e2deSReinhard Arlt #define VME_AM_Axx 0x03 19052a0e2deSReinhard Arlt #define VME_AM_USR 0x04 19152a0e2deSReinhard Arlt #define VME_AM_SUP 0x08 19252a0e2deSReinhard Arlt #define VME_AM_DATA 0x10 19352a0e2deSReinhard Arlt #define VME_AM_PROG 0x20 19452a0e2deSReinhard Arlt #define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG) 19552a0e2deSReinhard Arlt 19652a0e2deSReinhard Arlt #define VME_FLAG_D8 0x01 19752a0e2deSReinhard Arlt #define VME_FLAG_D16 0x02 19852a0e2deSReinhard Arlt #define VME_FLAG_D32 0x03 19952a0e2deSReinhard Arlt #define VME_FLAG_Dxx 0x03 20052a0e2deSReinhard Arlt 20152a0e2deSReinhard Arlt #endif 202