Home
last modified time | relevance | path

Searched refs:caches (Results 1 – 25 of 206) sorted by relevance

123456789

/openbmc/qemu/hw/virtio/
H A Dvirtio.c215 g_free(caches); in virtio_free_region_cache()
222 caches = qatomic_read(&vq->vring.caches); in virtio_virtqueue_reset_region_cache()
224 if (caches) { in virtio_virtqueue_reset_region_cache()
359 if (!caches) { in vring_avail_flags()
372 if (!caches) { in vring_avail_idx()
386 if (!caches) { in vring_avail_ring()
406 if (!caches) { in vring_used_write()
422 if (!caches) { in vring_used_flags()
435 if (!caches) { in vring_used_idx()
448 if (caches) { in vring_used_idx_set()
[all …]
/openbmc/linux/tools/cgroup/
H A Dmemcg_slabinfo.py184 caches = {}
203 caches[addr] = cache
215 for addr in caches:
217 cache_show(caches[addr], cfg, stats[addr])
/openbmc/linux/kernel/bpf/
H A Dmemalloc.c558 ma->caches = pcc; in bpf_mem_alloc_init()
605 if (ma->caches) { in check_leaked_objs()
607 cc = per_cpu_ptr(ma->caches, cpu); in check_leaked_objs()
620 free_percpu(ma->caches); in free_mem_alloc_no_barrier()
622 ma->caches = NULL; in free_mem_alloc_no_barrier()
698 if (ma->caches) { in bpf_mem_alloc_destroy()
701 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy()
829 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc()
846 unit_free(this_cpu_ptr(ma->caches)->cache + idx, ptr); in bpf_mem_free()
862 unit_free_rcu(this_cpu_ptr(ma->caches)->cache + idx, ptr); in bpf_mem_free_rcu()
/openbmc/linux/Documentation/block/
H A Dwriteback_cache_control.rst9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead-xscale.S28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
H A Dhead-sa1100.S38 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
40 @ disabling MMU and caches
/openbmc/linux/Documentation/filesystems/
H A D9p.rst80 cache=mode specifies a caching policy. By default, no caches are used.
86 0b00000000 all caches disabled, mmap disabled
87 0b00000001 file caches enabled
88 0b00000010 meta-data caches enabled
90 0b00001000 loose caches (no explicit consistency with server)
100 loose 0b00001111 (non-coherent file and meta-data caches)
108 IMPORTANT: loose caches (and by extension at the moment fscache)
184 /sys/fs/9p/caches. (applies only to cache=fscache)
/openbmc/linux/arch/arm/mm/
H A Dproc-arm720.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
H A Dproc-sa110.S49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
H A Dproc-fa526.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm926.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-sa1100.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-mohawk.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
359 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
H A Dproc-arm920.S61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm740.S40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
/openbmc/openbmc/poky/meta/classes-recipe/
H A Dmanpages.bbclass22 # only update manual page index caches when manual files are built and installed
37 # only update manual page index caches when manual files are built and installed
/openbmc/u-boot/doc/
H A DREADME.mips32 or override do_bootelf_exec() not to disable I-/D-caches, because most
33 Linux/MIPS ports don't re-enable caches after entering kernel_entry.
/openbmc/linux/include/linux/
H A Dbpf_mem_alloc.h12 struct bpf_mem_caches __percpu *caches; member
/openbmc/qemu/contrib/plugins/
H A Dcache.c287 Cache **caches; in caches_init() local
294 caches = g_new(Cache *, cores); in caches_init()
297 caches[i] = cache_init(blksize, assoc, cachesize); in caches_init()
300 return caches; in caches_init()
529 static void caches_free(Cache **caches) in caches_free() argument
534 cache_free(caches[i]); in caches_free()
/openbmc/linux/tools/perf/
H A Dbuiltin-stat.c1341 struct cpu_cache_level caches[MAX_CACHE_LVL]; in cpu__get_cache_details() local
1347 ret = build_caches_for_cpu(cpu.cpu, caches, &caches_cnt); in cpu__get_cache_details()
1371 if (caches[i].level > caches[max_level_index].level) in cpu__get_cache_details()
1375 cache->cache_lvl = caches[max_level_index].level; in cpu__get_cache_details()
1384 if (caches[i].level == cache_level) { in cpu__get_cache_details()
1389 cpu_cache_level__free(&caches[i]); in cpu__get_cache_details()
1397 cpu_cache_level__free(&caches[i++]); in cpu__get_cache_details()
1690 struct cpu_cache_level *caches = env->caches; in perf_env__get_cache_id_for_cpu() local
1710 cpu_map = perf_cpu_map__new(caches[i].map); in perf_env__get_cache_id_for_cpu()
1715 id->cache_lvl = caches[i].level; in perf_env__get_cache_id_for_cpu()
[all …]
/openbmc/linux/arch/openrisc/
H A DKconfig81 bool "Have write through data caches"
84 Select this if your implementation features write through data caches.
86 caches at relevant times. Most OpenRISC implementations support write-
87 through data caches.
/openbmc/openbmc/poky/meta/recipes-graphics/menu-cache/
H A Dmenu-cache_1.1.0.bb2 DESCRIPTION = "A library creating and utilizing caches to speed up freedesktop.org application menu…
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-support/libmediaart/
H A Dlibmediaart-2.0_1.9.6.bb1 SUMMARY = "Library tasked with managing, extracting and handling media art caches"
/openbmc/qemu/docs/
H A Dqcow2-cache.txt11 The QEMU qcow2 driver has two caches that can improve the I/O
16 caches, and how to configure them.
83 caches (in bytes) is:
121 "cache-size": maximum size of both caches combined
125 - Both caches must have a size that is a multiple of the cluster size
155 L2 cache size. This resulted in unnecessarily large caches, so now the
/openbmc/linux/drivers/acpi/numa/
H A Dhmat.c66 struct list_head caches; member
141 INIT_LIST_HEAD(&target->caches); in alloc_memory_target()
414 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
697 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
793 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()

123456789