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Searched refs:cacheline (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/net/fsl-mc/dpio/
H A Dqbman_portal.h128 const uint32_t *cacheline) in qb_attr_code_decode() argument
130 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
136 uint32_t *cacheline, uint32_t val) in qb_attr_code_encode() argument
138 cacheline[code->word] = in qb_attr_code_encode()
139 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
144 uint64_t *cacheline, uint64_t val) in qb_attr_code_encode_64() argument
146 cacheline[code->word / 2] = val; in qb_attr_code_encode_64()
/openbmc/u-boot/drivers/smem/
H A Dmsm_smem.c152 __le32 cacheline; member
265 size_t cacheline[SMEM_HOST_COUNT]; member
281 size_t cacheline) in phdr_to_first_cached_entry() argument
285 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*phdr), cacheline); in phdr_to_first_cached_entry()
313 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
317 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
492 size_t cacheline, in qcom_smem_get_private() argument
518 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
533 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
568 cacheln = __smem->cacheline[host]; in qcom_smem_get()
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/openbmc/openbmc/poky/bitbake/lib/bb/
H A Dcodeparser.py190 cacheline = pythonCacheLine(refs, execs, contains, extra)
191 h = hash(cacheline)
194 self.pythoncachelines[h] = cacheline
195 return cacheline
198 cacheline = shellCacheLine(execs)
199 h = hash(cacheline)
202 self.shellcachelines[h] = cacheline
203 return cacheline
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/libhugetlbfs/files/
H A D0008-alloc.c-Avoid-sysconf-_SC_LEVEL2_CACHE_LINESIZE-on-l.patch41 /* Lookup our cacheline size once */
/openbmc/qemu/target/hexagon/imported/
H A Dsystem.idef46 …TTRIBS(A_STORE,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); …
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr70 # cacheline interleaving
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
/openbmc/u-boot/include/configs/
H A DT4240QDS.h495 #define CTRL_INTLV_PREFERED cacheline
H A DT4240RDB.h637 #define CTRL_INTLV_PREFERED cacheline
H A DT208xRDB.h179 #define CTRL_INTLV_PREFERED cacheline
H A DT208xQDS.h194 #define CTRL_INTLV_PREFERED cacheline