| /openbmc/u-boot/drivers/net/fsl-mc/dpio/ |
| H A D | qbman_portal.h | 128 const uint32_t *cacheline) in qb_attr_code_decode() argument
130 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
136 uint32_t *cacheline, uint32_t val) in qb_attr_code_encode() argument
138 cacheline[code->word] = in qb_attr_code_encode()
139 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
144 uint64_t *cacheline, uint64_t val) in qb_attr_code_encode_64() argument
146 cacheline[code->word / 2] = val; in qb_attr_code_encode_64()
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | perf-c2c.txt | 20 you to track down the cacheline contentions.
88 Specify sorting fields for single cacheline display.
134 Group the detection of shared cacheline events into double cacheline
136 feature, which causes cacheline sharing to behave like the cacheline
141 The perf c2c record command setup options related to HITM cacheline analysis
177 - sort all the data based on the cacheline address
178 - store access details for each cacheline
184 2) offsets details for each cacheline
186 For each cacheline in the 1) list we display following data:
190 - zero based index to identify the cacheline
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| H A D | tips.txt | 37 To report cacheline events from previous recording: perf c2c report
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ring.h | 111 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
112 GEM_BUG_ON(cacheline(tail) == cacheline(head) && tail < head); in assert_ring_tail_valid()
113 #undef cacheline in assert_ring_tail_valid()
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| H A D | selftest_timeline.c | 97 unsigned long cacheline; in __mock_hwsp_timeline() local
110 cacheline = hwsp_cacheline(tl); in __mock_hwsp_timeline()
111 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
115 cacheline); in __mock_hwsp_timeline()
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| /openbmc/u-boot/drivers/smem/ |
| H A D | msm_smem.c | 152 __le32 cacheline; member
265 size_t cacheline[SMEM_HOST_COUNT]; member
281 size_t cacheline) in phdr_to_first_cached_entry() argument
285 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*phdr), cacheline); in phdr_to_first_cached_entry()
313 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
317 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
492 size_t cacheline, in qcom_smem_get_private() argument
518 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
533 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
568 cacheln = __smem->cacheline[host]; in qcom_smem_get()
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| /openbmc/linux/include/asm-generic/ |
| H A D | vmlinux.lds.h | 1013 #define PERCPU_INPUT(cacheline) \ argument
1018 . = ALIGN(cacheline); \
1020 . = ALIGN(cacheline); \
1050 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
1053 PERCPU_INPUT(cacheline) \
1069 #define PERCPU_SECTION(cacheline) \ argument
1073 PERCPU_INPUT(cacheline) \
1095 #define RW_DATA(cacheline, pagealigned, inittask) \ argument
1101 CACHELINE_ALIGNED_DATA(cacheline) \
1102 READ_MOSTLY_DATA(cacheline) \
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| /openbmc/linux/drivers/soc/qcom/ |
| H A D | smem.c | 155 __le32 cacheline; member
209 size_t cacheline; member
301 size_t cacheline) in phdr_to_first_cached_entry() argument
306 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline); in phdr_to_first_cached_entry()
335 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
339 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
629 e = phdr_to_first_cached_entry(phdr, part->cacheline); in qcom_smem_get_private()
657 e = cached_entry_next(e, part->cacheline); in qcom_smem_get_private()
978 smem->global_partition.cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_set_global_partition()
1031 smem->partitions[remote_host].cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_enumerate_partitions()
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| /openbmc/openbmc/poky/bitbake/lib/bb/ |
| H A D | codeparser.py | 182 cacheline = pythonCacheLine(refs, execs, contains, extra)
183 h = hash(cacheline)
186 self.pythoncachelines[h] = cacheline
187 return cacheline
190 cacheline = shellCacheLine(execs)
191 h = hash(cacheline)
194 self.shellcachelines[h] = cacheline
195 return cacheline
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| /openbmc/linux/drivers/md/bcache/ |
| H A D | bset.c | 526 unsigned int cacheline, in cacheline_to_bkey() argument
529 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
538 unsigned int cacheline, in bkey_to_cacheline_offset() argument
541 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
558 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned int cacheline) in table_to_bkey() argument
560 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
694 unsigned int j, cacheline = 1; in bch_bset_build_written_tree() local
715 while (bkey_to_cacheline(t, k) < cacheline) { in bch_bset_build_written_tree()
721 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
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| /openbmc/openbmc/poky/meta/recipes-devtools/gcc/gcc/ |
| H A D | 0027-gcc-backport-patch-to-fix-data-relocation-to-ENDBR-s.patch | 45 +/* When a hot loop can be fit into one cacheline,
179 + /* Skip bb which already fits into one cacheline. */
272 -/* When a hot loop can be fit into one cacheline,
406 - /* Skip bb which already fits into one cacheline. */
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| /openbmc/linux/Documentation/translations/zh_CN/locking/ |
| H A D | mutex-design.rst | 60 （cacheline bouncing）这种昂贵的开销。一个类MCS锁是为实现睡眠锁的
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/libhugetlbfs/files/ |
| H A D | 0008-alloc.c-Avoid-sysconf-_SC_LEVEL2_CACHE_LINESIZE-on-l.patch | 41 /* Lookup our cacheline size once */
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| /openbmc/linux/kernel/ |
| H A D | Kconfig.hz | 14 contention and cacheline bounces as a result of timer interrupts.
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| /openbmc/linux/Documentation/arch/sparc/ |
| H A D | adi.rst | 35 size is same as cacheline size which is 64 bytes. A task that sets ADI
103 the corresponding cacheline, a memory corruption trap occurs. By
123 the corresponding cacheline, a memory corruption trap occurs. If
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | system.idef | 46 …TTRIBS(A_STORE,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); …
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| /openbmc/linux/arch/sparc/kernel/ |
| H A D | prom_irqtrans.c | 356 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
367 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| H A D | cherrs.S | 203 sub %g1, %g2, %g1 ! Move down 1 cacheline
215 subcc %g1, %g2, %g1 ! Next cacheline
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| /openbmc/u-boot/doc/ |
| H A D | README.fsl-ddr | 70 # cacheline interleaving
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
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| /openbmc/linux/Documentation/translations/zh_CN/core-api/ |
| H A D | cachetlb.rst | 196 加载到不同的cacheline中就会出现别名现象。
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| /openbmc/u-boot/include/configs/ |
| H A D | T4240QDS.h | 495 #define CTRL_INTLV_PREFERED cacheline
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| H A D | T4240RDB.h | 637 #define CTRL_INTLV_PREFERED cacheline
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| H A D | T208xRDB.h | 179 #define CTRL_INTLV_PREFERED cacheline
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| H A D | T208xQDS.h | 194 #define CTRL_INTLV_PREFERED cacheline
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| /openbmc/linux/arch/parisc/kernel/ |
| H A D | perf_asm.S | 132 ; Cacheline start (32-byte cacheline)
145 ; Cacheline start (32-byte cacheline)
|