Searched refs:cacheable (Results 1 – 12 of 12) sorted by relevance
43 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable44 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable45 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable46 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable47 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable49 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
61 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable62 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable63 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable64 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable65 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable67 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)65 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
53 PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or54 non-cacheable accesses to any guest physical addresses that the
45 cacheable.)
370 AmlMaxFixed max_fixed, AmlCacheable cacheable,376 AmlMaxFixed max_fixed, AmlCacheable cacheable,
121 * cacheable accesses. TCG_BAR_SC is required to provide this
106 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
103 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
1498 AmlMaxFixed max_fixed, AmlCacheable cacheable, in aml_dword_memory() argument1504 uint8_t flags = read_and_write | (cacheable << 1); in aml_dword_memory()1518 AmlMaxFixed max_fixed, AmlCacheable cacheable, in aml_qword_memory() argument1524 uint8_t flags = read_and_write | (cacheable << 1); in aml_qword_memory()
358 map-cacheable;
564 tell the CPU whether memory is cacheable and if so the cache write