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/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc123 …c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
125 …c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
127 …c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
131 …0:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
133 …0:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
135 …0:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
137 …0:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
139 …0:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
143 …0:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
145 …0:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
[all …]
/openbmc/linux/arch/arm/mm/
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
H A Dproc-arm946.S57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcache-v4wt.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
H A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
H A Dproc-arm940.S50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
H A Dproc-xsc3.S149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
H A Dproc-fa526.S108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
H A Dproc-arm925.S143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
403 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-arm926.S109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-mohawk.S92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
H A Dcache-v4wb.S58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
H A Dtlb-v6.S50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-xscale.S148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
237 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
244 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
268 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
285 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
290 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
311 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
473 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
H A Dproc-arm922.S110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
355 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-arm920.S108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
351 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
H A Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
H A Dproc-v6.S63 mcr p15, 0, r1, c7, c5, 4 @ ISB
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
156 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
172 mcr p15, 0, ip, c7, c5, 4 @ ISB
208 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
H A Dproc-feroceon.S127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
246 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
479 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-arm1020e.S118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
388 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
/openbmc/linux/arch/arm/include/asm/vdso/
H A Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/openbmc/qemu/tests/tcg/hexagon/
H A Dpreg_alias.c79 uint32_t c5; in creg_alias_pair() local
88 "=r"(pregs->pregs.p2), "=r"(pregs->pregs.p3), "=r"(c5) in creg_alias_pair()
92 check32(c5, 0xdeadbeef); in creg_alias_pair()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-suspend.S57 mcr p15, 0, r6, c7, c5, 0
58 mcr p15, 0, r6, c7, c5, 6

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