1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 284ad6884SPeter Tyser/* 384ad6884SPeter Tyser * armboot - Startup Code for ARM926EJS CPU-core 484ad6884SPeter Tyser * 584ad6884SPeter Tyser * Copyright (c) 2003 Texas Instruments 684ad6884SPeter Tyser * 784ad6884SPeter Tyser * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 884ad6884SPeter Tyser * 9fa82f871SAlbert ARIBAUD * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 10fa82f871SAlbert ARIBAUD * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 1184ad6884SPeter Tyser * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 1284ad6884SPeter Tyser * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 1384ad6884SPeter Tyser * Copyright (c) 2003 Kshitij <kshitij@ti.com> 1457b4bce9SAlbert ARIBAUD * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 1584ad6884SPeter Tyser */ 1684ad6884SPeter Tyser 1725ddd1fbSWolfgang Denk#include <asm-offsets.h> 1884ad6884SPeter Tyser#include <config.h> 1984ad6884SPeter Tyser#include <common.h> 2084ad6884SPeter Tyser 2184ad6884SPeter Tyser/* 2284ad6884SPeter Tyser ************************************************************************* 2384ad6884SPeter Tyser * 2484ad6884SPeter Tyser * Startup Code (reset vector) 2584ad6884SPeter Tyser * 2684ad6884SPeter Tyser * do important init only if we don't start from memory! 2784ad6884SPeter Tyser * setup Memory and board specific bits prior to relocation. 2884ad6884SPeter Tyser * relocate armboot to ram 2984ad6884SPeter Tyser * setup stack 3084ad6884SPeter Tyser * 3184ad6884SPeter Tyser ************************************************************************* 3284ad6884SPeter Tyser */ 3384ad6884SPeter Tyser 3441623c91SAlbert ARIBAUD .globl reset 35ab86f72cSHeiko Schocher 36ab86f72cSHeiko Schocherreset: 37ab86f72cSHeiko Schocher /* 38ab86f72cSHeiko Schocher * set the cpu to SVC32 mode 39ab86f72cSHeiko Schocher */ 40ab86f72cSHeiko Schocher mrs r0,cpsr 41ab86f72cSHeiko Schocher bic r0,r0,#0x1f 42ab86f72cSHeiko Schocher orr r0,r0,#0xd3 43ab86f72cSHeiko Schocher msr cpsr,r0 44ab86f72cSHeiko Schocher 45ab86f72cSHeiko Schocher /* 46ab86f72cSHeiko Schocher * we do sys-critical inits only at reboot, 47ab86f72cSHeiko Schocher * not when booting from ram! 48ab86f72cSHeiko Schocher */ 4927b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 50ab86f72cSHeiko Schocher bl cpu_init_crit 5127b66622SChristian Riesch#endif 52ab86f72cSHeiko Schocher 53e05e5de7SAlbert ARIBAUD bl _main 54ab86f72cSHeiko Schocher 55ab86f72cSHeiko Schocher/*------------------------------------------------------------------------------*/ 56ab86f72cSHeiko Schocher 57e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 58e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 59e05e5de7SAlbert ARIBAUD 60e05e5de7SAlbert ARIBAUD bx lr 61e05e5de7SAlbert ARIBAUD 6284ad6884SPeter Tyser/* 6384ad6884SPeter Tyser ************************************************************************* 6484ad6884SPeter Tyser * 6584ad6884SPeter Tyser * CPU_init_critical registers 6684ad6884SPeter Tyser * 6784ad6884SPeter Tyser * setup important registers 6884ad6884SPeter Tyser * setup memory timing 6984ad6884SPeter Tyser * 7084ad6884SPeter Tyser ************************************************************************* 7184ad6884SPeter Tyser */ 7227b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 7384ad6884SPeter Tysercpu_init_crit: 7484ad6884SPeter Tyser /* 75da104e04SSughosh Ganu * flush D cache before disabling it 7684ad6884SPeter Tyser */ 7784ad6884SPeter Tyser mov r0, #0 78da104e04SSughosh Ganuflush_dcache: 79da104e04SSughosh Ganu mrc p15, 0, r15, c7, c10, 3 80da104e04SSughosh Ganu bne flush_dcache 81da104e04SSughosh Ganu 82da104e04SSughosh Ganu mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 83da104e04SSughosh Ganu mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 8484ad6884SPeter Tyser 8584ad6884SPeter Tyser /* 86d735a99dSChristian Riesch * disable MMU and D cache 87d735a99dSChristian Riesch * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 8884ad6884SPeter Tyser */ 8984ad6884SPeter Tyser mrc p15, 0, r0, c1, c0, 0 90b67d8816SChristian Riesch bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 9184ad6884SPeter Tyser bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 92b67d8816SChristian Riesch#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 93b67d8816SChristian Riesch orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 94b67d8816SChristian Riesch#else 95b67d8816SChristian Riesch bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 96b67d8816SChristian Riesch#endif 97ba10b852SYuichiro Goto orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 98d735a99dSChristian Riesch#ifndef CONFIG_SYS_ICACHE_OFF 9984ad6884SPeter Tyser orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 100d735a99dSChristian Riesch#endif 10184ad6884SPeter Tyser mcr p15, 0, r0, c1, c0, 0 10284ad6884SPeter Tyser 103b5bd0982SSimon Glass#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 10484ad6884SPeter Tyser /* 10584ad6884SPeter Tyser * Go setup Memory and board specific bits prior to relocation. 10684ad6884SPeter Tyser */ 107da372af6SMans Rullgard mov r4, lr /* perserve link reg across call */ 10884ad6884SPeter Tyser bl lowlevel_init /* go setup pll,mux,memory */ 109da372af6SMans Rullgard mov lr, r4 /* restore link */ 110b5bd0982SSimon Glass#endif 111ca4b5580SHeiko Schocher mov pc, lr /* back to my caller */ 11227b66622SChristian Riesch#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 113