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/openbmc/u-boot/board/keymile/kmp204x/
H A Dpbi.cfg10 091380c0 000009C4
12 091380c0 000009C4
14 091380c0 000009C4
17 091380c0 000009C4
19 091380c0 000009C4
21 091380c0 000009C4
23 091380c0 000009C4
25 091380c0 000009C4
27 091380c0 000009C4
29 091380c0 000009C4
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/openbmc/phosphor-webui/app/assets/images/
H A DDMTF_Redfish_logo_2017.svg1 …c0 2.2.3 4.1 1 5.8.7 1.7 1.6 3.2 2.9 4.6 2.4 2.5 5.5 3.7 9.4 3.7 3.5 0 6.4-.7 8.7-2.2 2.3-1.5 4.3-…
/openbmc/qemu/tests/tcg/s390x/
H A Dsckc.S20 stctg %c0,%c0,c0
21 oi c0+6,8 /* set clock-comparator subclass mask */
22 lctlg %c0,%c0,c0
56 c0: label
H A Dprecise-smc-softmmu.S15 lctlg %c0,%c0,c0
58 c0: label
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
66 mcrne p15, 1, r0, c9, c0, 2
72 mrc p15, 0, r0, c1, c0, 1
74 mcr p15, 0, r0, c1, c0, 1
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S84 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
109 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
111 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
116 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
191 mrc p15, 0, r0, c1, c0, 0
201 mcr p15, 0, r0, c1, c0, 0
204 mrc p15, 0, r0, c1, c0, 0 @ read system control register
206 mcr p15, 0, r0, c1, c0, 0 @ write system control register
210 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
212 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
[all …]
H A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
109 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
111 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
H A Dnonsec_virt.S32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
48 mcr p15, 0, r5, c12, c0, 1
61 mrc p15, 0, r5, c1, c0, 1
63 mcr p15, 0, r5, c1, c0, 1
68 mrc p15, 0, r5, c1, c0, 1
70 mcr p15, 0, r5, c1, c0, 1
93 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
118 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
193 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
197 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
[all …]
H A Dpsci.S183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
232 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
240 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
242 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
250 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
252 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
265 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
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/openbmc/webui-vue/src/assets/images/
H A Dbuilt-on-openbmc-logo.svg3 ….529-.561 2.294a27.54 27.54 0 00-.867 6.553c0 15.487 12.556 28.044 28.044 28.044s28.044-12.557 28.…
6 ….179c-15.327-2.225-29.557 8.397-31.781 23.725a28.227 28.227 0 00-.291 4.014c0 15.488 12.557 28.044…
8 …c0-18.814-15.985-34.061-35.693-34.061-19.707 0-35.692 15.297-35.692 34.061 0 18.765 15.985 34.062 …
11 …c0-1.813-.528-3.238-1.585-4.271s-2.722-1.551-4.996-1.551H113.21l-2.272 13.193zm3.786-21.978h6.513c…
H A Dlogo-header.svg1 …c0 .401-.051.77-.154 1.106a2.705 2.705 0 01-.434.868 1.946 1.946 0 01-.693.567 2.083 2.083 0 01-.9…
/openbmc/docs/logo/
H A DBuiltOnOpenBMC.svg3 ….529-.561 2.294a27.54 27.54 0 00-.867 6.553c0 15.487 12.556 28.044 28.044 28.044s28.044-12.557 28.…
6 ….179c-15.327-2.225-29.557 8.397-31.781 23.725a28.227 28.227 0 00-.291 4.014c0 15.488 12.557 28.044…
8 …c0-18.814-15.985-34.061-35.693-34.061-19.707 0-35.692 15.297-35.692 34.061 0 18.765 15.985 34.062 …
11 …c0-1.813-.528-3.238-1.585-4.271s-2.722-1.551-4.996-1.551H113.21l-2.272 13.193zm3.786-21.978h6.513c…
/openbmc/qemu/tests/tcg/multiarch/
H A Dcatch-syscalls.c19 char c0 = 'A', c1; in main() local
28 if (write(fd[1], &c0, sizeof(c0)) != sizeof(c0)) { in main()
38 if (c0 == c1) { in main()
/openbmc/qemu/pc-bios/s390-ccw/
H A Dstart.S69 stctg %c0,%c0,0(%r15)
71 lctlg %c0,%c0,0(%r15)
103 stctg %c0,%c0,0(%r15)
105 lctlg %c0,%c0,0(%r15)
/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
21 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
23 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
35 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
37 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 mcr p15, 0, r0, c1, c0, 0
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
44 mcr p15, 0, r0, c1, c0, 0
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
56 mcr p15, 0, r0, c2, c0, 2
59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
76 mcr p15, 0, r0, c1, c0, 0
H A Dpsci_smp.S14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
/openbmc/u-boot/board/freescale/t104xrdb/
H A Dt104x_pbi_sb.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
38 091380c0 000FFFFF
H A Dt104x_pbi.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-suspend.S19 mcr p15, 2, r0, c0, c0, 0
20 mrc p15, 1, r0, c0, c0, 0
61 mcr p15, 0, r6, c1, c0, 0
/openbmc/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dlowlevel_init.S28 mcr p15, 0, r0, c14, c0, 0
31 mrc p15, 0, r0, c1, c0, 1
33 mcr p15, 0, r0, c1, c0, 1
36 mrc p15, 0, r0, c0, c0, 5
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dstart.S107 mrc p15, 0, r0, c1, c0, 0
111 mcr p15, 0, r0, c1, c0, 0
124 mrc p15, 0, \reg, c2, c0, 0
131 mcr p15, 0, r0, c3, c0, 0
135 mcr p15, 0, r0, c2, c0, 0
138 mrc p15, 0, r0, c1, c0, 0
143 mcr p15, 0, r0, c1, c0, 0
/openbmc/u-boot/arch/arm/dts/
H A Dstih410-clock.dtsi88 clk_ext2f_a9: clockgen-c0@13 {
123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
130 clock-output-names = "clk-s-c0-fs0-ch0",
131 "clk-s-c0-fs0-ch1",
132 "clk-s-c0-fs0-ch2",
133 "clk-s-c0-fs0-ch3";
134 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
141 clk_s_c0_pll0: clk-s-c0-pll0 {
147 clock-output-names = "clk-s-c0-pll0-odf-0";
148 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
[all …]
H A Dstih407-clock.dtsi86 clk_ext2f_a9: clockgen-c0@13 {
118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
125 clock-output-names = "clk-s-c0-fs0-ch0",
126 "clk-s-c0-fs0-ch1",
127 "clk-s-c0-fs0-ch2",
128 "clk-s-c0-fs0-ch3";
135 clk_s_c0_pll0: clk-s-c0-pll0 {
141 clock-output-names = "clk-s-c0-pll0-odf-0";
144 clk_s_c0_pll1: clk-s-c0-pll1 {
150 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
/openbmc/webui-vue/tests/unit/__snapshots__/
H A DAppNavigation.spec.js.snap275 <path d="M13.5,8.4c0-0.1,0-0.3,0-0.4c0-0.1,0-0.3,0-0.4l1-0.8c0.4-0.3,0.4-0.9,0.2-1.3l-1.2-2C13.3,3.2,13,3,12.6,3 c-0.1,0-0.2,0-0.3,0.1l-1.2,0.4c-0.2-0.1-0.4-0.3-0.7-0.4l-0.3-1.3C10.1,1.3,9.7,1,9.2,1H6.8c-0.5,0-0.9,0.3-1,0.8L5.6,3.1 C5.3,3.2,5.1,3.3,4.9,3.4L3.7,3C3.6,3,3.5,3,3.4,3C3,3,2.7,3.2,2.5,3.5l-1.2,2C1.1,5.9,1.2,6.4,1.6,6.8l0.9,0.9c0,0.1,0,0.3,0,0.4 c0,0.1,0,0.3,0,0.4L1.6,9.2c-0.4,0.3-0.5,0.9-0.2,1.3l1.2,2C2.7,12.8,3,13,3.4,13c0.1,0,0.2,0,0.3-0.1l1.2-0.4 c0.2,0.1,0.4,0.3,0.7,0.4l0.3,1.3c0.1,0.5,0.5,0.8,1,0.8h2.4c0.5,0,0.9-0.3,1-0.8l0.3-1.3c0
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