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Searched refs:bwl0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c85 u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */ in mbus_configure_port() argument
97 | (bwl0 << 16) ); in mbus_configure_port()
105 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ argument
107 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
H A Ddram_sun50i_h6.c120 u16 bwl0, in mbus_configure_port() argument
132 | (bwl0 << 16) ); in mbus_configure_port()
140 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ argument
142 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)