Home
last modified time | relevance | path

Searched refs:buses (Results 1 – 25 of 47) sorted by relevance

12

/openbmc/entity-manager/docs/
H A Dblacklist_configuration.md3 The blacklist.json in package directory can determine i2c buses and addresses
8 ## For buses
10 Put in numbers of buses. For example:
14 "buses": [1, 3, 5]
18 Note that "buses" should be an array of unsigned integer.
26 "buses": [
57 "buses": [
H A Dmy_first_sensors.md67 The FruDevice daemon will walk all i2c buses and attempt to find FRU contents at
255 the configuration, which will trigger FruDevice to scan those new buses for more
/openbmc/openbmc/meta-ingrasys/meta-zaius/recipes-phosphor/chassis/avsbus-control/
H A Dzaius_avsbus.sh9 buses="$cpu0_i2c_bus $cpu1_i2c_bus"
40 for bus in $buses
/openbmc/u-boot/drivers/i2c/muxes/
H A DKconfig5 This enables I2C buses to be multiplexed, so that you can select
6 one of several buses using some sort of control mechanism. The
14 This enables I2C buses to be multiplexed, so that you can select
15 one of several buses using some sort of control mechanism. The
/openbmc/u-boot/doc/
H A DREADME.bitbangMII2 support an arbitrary number of mii buses. This feature is useful when your
3 board uses different mii buses for different phys and all (or a part) of these
4 buses are implemented via bit-banging mode.
29 the bb_miiphy_buses_num variable with the number of mii buses.
H A DREADME.i2c4 While I2C supports multi-master buses this is difficult to get right.
H A DREADME.virtio22 VirtIO can use various different buses, aka transports as described in the
56 MMIO and PCI buses. In this case, you can enable the PCI transport driver
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dfsl-tsec-phy.txt48 This PHY is accessed through the local MDIO bus. These buses are defined
49 similarly to the mdio buses. The TBI PHYs underneath them are similar to
/openbmc/qemu/hw/pci/
H A Dmeson.build15 # allow plugging PCIe devices into PCI buses, include them even if
/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt29 any device plugged in, has no free buses reserved to provide any of them
32 To solve this problem we reserve additional buses on a firmware level.
49 uint32_t bus_res; Minimum number of buses to reserve
H A Dpcie.txt198 Each PCI domain can have up to only 256 buses and the QEMU PCI Express
214 number space. All bus numbers assigned to the buses recursively behind a
222 The PCI Express root buses (pcie.0 and the buses exposed by pxb-pcie devices)
H A Dqdev-device-use.txt6 more buses for children. You can specify a device's parent bus with
9 A device typically has a device address on its parent bus. For buses
33 device. For instance, the IDE controller provides two IDE buses, each
52 TYPE, BUS and UNIT identify the controller device, which of its buses
H A Dpci_expander_bridge.txt8 the main host bridge to support multiple PCI root buses.
/openbmc/openpower-hw-diags/analyzer/ras-data/
H A Dras-data-definition.md41 ## 4) `buses` keyword
43 The value of this keyword is a JSON object representing all of the buses
144 | name | The `<bus_name>` as defined by the `buses` keyword. |
163 | name | The `<bus_name>` as defined by the `buses` keyword. |
/openbmc/qemu/docs/system/
H A Ddevice-emulation.rst33 machine model you choose (``-M foo``) a number of buses will have been
42 additional buses to the system that other devices can be attached to.
/openbmc/u-boot/drivers/dma/
H A DKconfig12 buses that is used to transfer data to and from memory.
/openbmc/qemu/docs/system/devices/
H A Dcan.rst4 emulated CAN controller chips together by one or multiple CAN buses
5 (the controller device "canbus" parameter). The individual buses
9 The concept of buses is generic and different CAN controllers
/openbmc/qemu/docs/specs/
H A Dfsi.rst13 FSI allows a service processor access to the internal buses of a host POWER
22 "engines" that drive accesses on buses internal and external to the POWER
/openbmc/qemu/docs/devel/
H A Dkconfig.rst16 Each QEMU target enables a subset of the boards, devices and buses that
141 **subsystems**, of which **buses** are a special case
153 subsystems or buses. For example, ``AUX`` (the DisplayPort auxiliary
172 have no ``depends on`` directive. Devices also *select* the buses
H A Dreset.rst266 for devices and buses and should be preferred.
358 child buses, and all the devices on those child buses.
/openbmc/qemu/docs/devel/testing/
H A Dqtest.rst31 communicating with system buses or devices. Many virtual device tests use
/openbmc/u-boot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt54 services. Put another way, the numbering scheme for I2C buses is distinct from
/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst87 * I3C buses (8XX only)
/openbmc/qemu/hw/ssi/
H A Dxilinx_spips.c256 uint8_t buses; in xlnx_zynqmp_qspips_update_cs_lines() local
259 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); in xlnx_zynqmp_qspips_update_cs_lines()
260 bus0_enabled = buses & 1; in xlnx_zynqmp_qspips_update_cs_lines()
261 bus1_enabled = buses & (1 << 1); in xlnx_zynqmp_qspips_update_cs_lines()
/openbmc/u-boot/drivers/pci/
H A DKconfig17 available PCI devices, allows scanning of PCI buses and provides

12