| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-brcmstb.c | 35 struct clk *base_clk; member
259 struct clk *base_clk = NULL; in sdhci_brcmstb_probe() local
334 if (IS_ERR(base_clk)) { in sdhci_brcmstb_probe()
339 res = clk_prepare_enable(base_clk); in sdhci_brcmstb_probe()
344 clk_set_rate(base_clk, priv->base_freq_hz); in sdhci_brcmstb_probe()
345 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; in sdhci_brcmstb_probe()
354 priv->base_clk = base_clk; in sdhci_brcmstb_probe()
366 clk_disable_unprepare(base_clk); in sdhci_brcmstb_probe()
384 clk_disable_unprepare(priv->base_clk); in sdhci_brcmstb_suspend()
397 ret = clk_prepare_enable(priv->base_clk); in sdhci_brcmstb_resume()
[all …]
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| H A D | sdhci-pic32.c | 48 struct clk *base_clk; member
55 return clk_get_rate(sdhci_pdata->base_clk); in pic32_sdhci_get_max_clock()
176 sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk"); in pic32_sdhci_probe()
177 if (IS_ERR(sdhci_pdata->base_clk)) { in pic32_sdhci_probe()
178 ret = PTR_ERR(sdhci_pdata->base_clk); in pic32_sdhci_probe()
183 ret = clk_prepare_enable(sdhci_pdata->base_clk); in pic32_sdhci_probe()
203 clk_disable_unprepare(sdhci_pdata->base_clk); in pic32_sdhci_probe()
221 clk_disable_unprepare(sdhci_pdata->base_clk); in pic32_sdhci_remove()
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| H A D | sdhci-sprd.c | 206 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) in sdhci_sprd_calc_div() argument
211 if (base_clk <= clk * 2) in sdhci_sprd_calc_div()
214 div = (u32) (base_clk / (clk * 2)); in sdhci_sprd_calc_div()
216 if ((base_clk / div) > (clk * 2)) in sdhci_sprd_calc_div()
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| /openbmc/linux/drivers/media/rc/ |
| H A D | sunxi-cir.c | 142 static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr) in sunxi_ithr_to_usec() argument
145 base_clk / (128 * 64)); in sunxi_ithr_to_usec()
149 static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec) in sunxi_usec_to_ithr() argument
152 return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1; in sunxi_usec_to_ithr()
158 unsigned int base_clk = clk_get_rate(ir->clk); in sunxi_ir_set_timeout() local
160 unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout); in sunxi_ir_set_timeout()
168 rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr); in sunxi_ir_set_timeout()
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-a10-pll2.c | 42 struct clk **clks, *base_clk, *prediv_clk; in sun4i_pll2_setup() local
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
101 if (IS_ERR(base_clk)) { in sun4i_pll2_setup()
106 parent = __clk_get_name(base_clk); in sun4i_pll2_setup()
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-samsung.c | 88 struct clk *base_clk; member
172 rate = clk_get_rate(chip->base_clk); in pwm_samsung_get_tin_rate()
587 chip->base_clk = devm_clk_get(&pdev->dev, "timers"); in pwm_samsung_probe()
588 if (IS_ERR(chip->base_clk)) { in pwm_samsung_probe()
590 return PTR_ERR(chip->base_clk); in pwm_samsung_probe()
593 ret = clk_prepare_enable(chip->base_clk); in pwm_samsung_probe()
612 clk_disable_unprepare(chip->base_clk); in pwm_samsung_probe()
617 clk_get_rate(chip->base_clk), in pwm_samsung_probe()
630 clk_disable_unprepare(chip->base_clk); in pwm_samsung_remove()
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-pic32-sqi.c | 141 struct clk *base_clk; /* drives spi clock */ member
170 div = clk_get_rate(sqi->base_clk) / (2 * sck); in pic32_sqi_set_clk_rate()
603 sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck"); in pic32_sqi_probe()
604 if (IS_ERR(sqi->base_clk)) { in pic32_sqi_probe()
605 ret = PTR_ERR(sqi->base_clk); in pic32_sqi_probe()
616 ret = clk_prepare_enable(sqi->base_clk); in pic32_sqi_probe()
645 host->max_speed_hz = clk_get_rate(sqi->base_clk); in pic32_sqi_probe()
673 clk_disable_unprepare(sqi->base_clk); in pic32_sqi_probe()
690 clk_disable_unprepare(sqi->base_clk); in pic32_sqi_remove()
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| H A D | spi-bcm-qspi.c | 225 u32 base_clk; member
653 qspi->base_clk = MSPI_BASE_FREQ; in bcm_qspi_hw_set_parms()
657 qspi->base_clk = MSPI_BASE_FREQ * 4; in bcm_qspi_hw_set_parms()
685 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); in bcm_qspi_hw_set_parms()
686 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp); in bcm_qspi_hw_set_parms()
1591 qspi->base_clk = clk_get_rate(qspi->clk); in bcm_qspi_probe()
1593 qspi->base_clk = MSPI_BASE_FREQ; in bcm_qspi_probe()
1607 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); in bcm_qspi_probe()
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | microchip,sdhci-pic32.txt | 9 - clock-names: Should be "base_clk", "sys_clk".
24 clock-names = "base_clk", "sys_clk";
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| /openbmc/linux/arch/arm/boot/dts/nspire/ |
| H A D | nspire.dtsi | 44 base_clk: base_clk { label
52 clocks = <&base_clk>;
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| H A D | nspire-classic.dtsi | 44 &base_clk {
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| H A D | nspire-cx.dts | 39 &base_clk {
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | nspire-clock.txt | 23 clocks = <&base_clk>;
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| /openbmc/u-boot/arch/mips/dts/ |
| H A D | pic32mzda.dtsi | 158 clock-names = "base_clk", "sys_clk";
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| /openbmc/linux/arch/mips/boot/dts/pic32/ |
| H A D | pic32mzda.dtsi | 233 clock-names = "base_clk", "sys_clk";
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