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Searched refs:bank0 (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S59 ! BL=0: R7->R0 is bank0
80 ! BL=0: R7->R0 is bank0
105 ! BL=0: R7->R0 is bank0
116 jsr @k1 ! switch to bank0 and save all regs
119 ! BL=0: R7->R0 is bank0
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt54 - compatible: "rockchip,rk3188-gpio-bank0"
55 - reg: second element: separate pull register for rk3188 bank0, use
130 compatible = "rockchip,rk3188-gpio-bank0";
/openbmc/linux/drivers/iommu/
H A Dmtk_iommu.c1021 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; in mtk_iommu_hw_init() local
1032 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1035 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1044 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
1047 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1049 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1053 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
1055 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
1062 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
1068 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
/openbmc/linux/drivers/video/fbdev/
H A Dplatinumfb.c533 int bank0, bank1, bank2, bank3, rc; in platinumfb_probe() local
595 bank0 = 1; /* builtin 1MB vram, always there */ in platinumfb_probe()
599 pinfo->total_vram = (bank0 + bank1 + bank2 + bank3) * 0x100000; in platinumfb_probe()
602 bank3, bank2, bank1, bank0); in platinumfb_probe()
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-msc-sm2s-14N0600E.dtsi12 reg = <0x0 0x40000000 0 0x80000000>; /* bank0, 2GiB */
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-is2.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-ns2l.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-memphis.cfg167 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
168 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
H A Dkwbimage_256M8_1.cfg244 # bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
245 # bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
H A Dkwbimage_128M16_1.cfg244 # bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
/openbmc/linux/Documentation/admin-guide/gpio/
H A Dgpio-sim.rst96 bank0 {
100 gpio-sim,label = "dt-bank0";
/openbmc/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh316 create_bank chip bank0
317 set_label chip bank0 foobar
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB82 => run boot_bank0 (boot from NOR bank0)
151 For bank0
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f469-disco-u-boot.dtsi48 bank0: bank@0 { label
H A Dstm32429i-eval-u-boot.dtsi48 bank0: bank@0 { label
H A Dbcm283x.dtsi153 * So, a bank0 interrupt shows up on 17, 20, and
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME198 Switching between default bank0 and alternate bank4 on NOR flash
212 via software: run command 'switch bank0' in U-Boot.
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c83 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); variable
568 REG_WRITE_ARRAY(&bank0, 1, regWrites); in ar5008_hw_set_rf_regs()
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm283x.dtsi118 * So, a bank0 interrupt shows up on 17, 20, and
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME173 Switching between default bank0 and alternate bank4 on NOR flash
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME222 Switching between default bank0 and alternate bank4 on NOR flash
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi228 compatible = "rockchip,rk3188-gpio-bank0";

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