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Searched refs:amdgpu_reset_control (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_reset.h48 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
50 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
52 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
54 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
56 int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
62 struct amdgpu_reset_control { struct
70 struct amdgpu_reset_control *reset_ctl, argument
100 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
H A Dsmu_v13_0_10.c32 static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl) in smu_v13_0_10_is_mode2_default()
42 smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl, in smu_v13_0_10_get_reset_handler()
99 smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, in smu_v13_0_10_mode2_prepare_hwcontext()
119 struct amdgpu_reset_control *reset_ctl = in smu_v13_0_10_async_reset()
120 container_of(work, struct amdgpu_reset_control, reset_work); in smu_v13_0_10_async_reset()
133 smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, in smu_v13_0_10_mode2_perform_reset()
231 smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, in smu_v13_0_10_mode2_restore_hwcontext()
277 struct amdgpu_reset_control *reset_ctl; in smu_v13_0_10_reset_init()
H A Dsienna_cichlid.c34 static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl) in sienna_cichlid_is_mode2_default()
47 sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, in sienna_cichlid_get_reset_handler()
100 sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, in sienna_cichlid_mode2_prepare_hwcontext()
120 struct amdgpu_reset_control *reset_ctl = in sienna_cichlid_async_reset()
121 container_of(work, struct amdgpu_reset_control, reset_work); in sienna_cichlid_async_reset()
142 sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, in sienna_cichlid_mode2_perform_reset()
236 sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, in sienna_cichlid_mode2_restore_hwcontext()
286 struct amdgpu_reset_control *reset_ctl; in sienna_cichlid_reset_init()
H A Daldebaran.c34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) in aldebaran_is_mode2_default()
46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, in aldebaran_get_reset_handler()
107 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, in aldebaran_mode2_prepare_hwcontext()
124 struct amdgpu_reset_control *reset_ctl = in aldebaran_async_reset()
125 container_of(work, struct amdgpu_reset_control, reset_work); in aldebaran_async_reset()
147 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, in aldebaran_mode2_perform_reset()
331 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, in aldebaran_mode2_restore_hwcontext()
424 struct amdgpu_reset_control *reset_ctl; in aldebaran_reset_init()
H A Damdgpu_reset.c29 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl, in amdgpu_reset_add_handler()
H A Damdgpu.h298 struct amdgpu_reset_control;
1055 struct amdgpu_reset_control *reset_cntl;