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Searched refs:additive_latency (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/ddr/fsl/
H A Dlc_common_dimm_params.c257 unsigned int additive_latency = 0; in compute_lowest_common_dimm_parameters() local
522 additive_latency = 0; in compute_lowest_common_dimm_parameters()
528 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) - in compute_lowest_common_dimm_parameters()
530 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { in compute_lowest_common_dimm_parameters()
531 additive_latency = picos_to_mclk(ctrl_num, trcd_ps); in compute_lowest_common_dimm_parameters()
533 " greater than tRCD_ps\n", additive_latency); in compute_lowest_common_dimm_parameters()
543 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { in compute_lowest_common_dimm_parameters()
561 outpdimm->additive_latency = additive_latency; in compute_lowest_common_dimm_parameters()
H A Dctrl_regs.c458 unsigned int additive_latency) in set_timing_cfg_3() argument
481 ext_add_lat = additive_latency >> 4; in set_timing_cfg_3()
638 unsigned int additive_latency) in set_timing_cfg_2() argument
659 add_lat_mclk = additive_latency; in set_timing_cfg_2()
1352 unsigned int additive_latency, in set_ddr_sdram_mode() argument
1523 unsigned int additive_latency, in set_ddr_sdram_mode() argument
1761 al = additive_latency; in set_ddr_sdram_mode()
2357 unsigned int additive_latency; in compute_fsl_memctl_config_regs() local
2415 : common_dimm->additive_latency; in compute_fsl_memctl_config_regs()
2556 additive_latency); in compute_fsl_memctl_config_regs()
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H A Dinteractive.c193 COMMON_TIMING(additive_latency), in lowest_common_dimm_parameters_edit()
467 COMMON_TIMING(additive_latency), in print_lowest_common_dimm_parameters()
/openbmc/u-boot/include/
H A Dcommon_timing_params.h55 unsigned int additive_latency; member
/openbmc/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c335 u32 additive_latency, mcas_to_preamble_override, write_latency, in mpc83xx_sdram_probe() local
693 additive_latency = dev_read_u32_default(dev, "additive_latency", 0); in mpc83xx_sdram_probe()
694 if (additive_latency > 5) { in mpc83xx_sdram_probe()
696 dev->name, additive_latency); in mpc83xx_sdram_probe()
777 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | in mpc83xx_sdram_probe()
/openbmc/u-boot/Documentation/devicetree/bindings/ram/
H A Dfsl,mpc83xx-mem-controller.txt105 - additive_latency: Additive latency; possible values:
280 additive_latency = <0>;