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/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Drzg2lc-smarc.dtsi146 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
147 * SW2 should be at position 2->3 so that SER0_TX line is activated
148 * SW3 should be at position 2->3 so that SER0_RX line is activated
149 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
H A Drzg2l-smarc.dtsi137 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
138 * SW2 should be at position 2->3 so that SER0_TX line is activated
139 * SW3 should be at position 2->3 so that SER0_RX line is activated
140 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
H A Drzg2l-smarc-pinfunction.dtsi20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
33 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
H A Dr8a774e1-hihope-rzg2h-ex.dts17 /* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
H A Dr8a774a1-hihope-rzg2m-ex.dts18 /* SW43 should be OFF, if in ON state SATA port will be activated */
H A Dr8a774b1-hihope-rzg2n-ex.dts18 /* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
H A Dr8a774a1-hihope-rzg2m-rev2-ex.dts17 /* SW43 should be OFF, if in ON state SATA port will be activated */
/openbmc/telemetry/src/
H A Dstate.hpp15 activated, enumerator
42 return StateEvent::activated; in set()
/openbmc/linux/drivers/ntb/hw/idt/
H A DKconfig16 First of all partitions must be activated and properly assigned to all
17 the ports with NT-functions intended to be activated (see SWPARTxCTL
/openbmc/linux/fs/ntfs3/
H A DKconfig22 If activated 64 bits per clusters you will be able to use 4k cluster
33 If activated you will be able to read such files correctly.
/openbmc/qemu/
H A D.exrc1 "VIM settings to match QEMU coding style. They are activated by adding the
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Datmel-usb.txt17 activated for the bus to be powered.
19 activated for the overcurrent detection.
71 activated for the bus to be powered.
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/
H A Dtrusted-firmware-a.inc53 # add MBEDTLS to our sources if activated
62 # When U-Boot support is activated BL33 is activated with u-boot.bin file
66 # When UEFI support is activated BL33 is activated with uefi.bin file
/openbmc/linux/drivers/thunderbolt/
H A Dpath.c160 path->activated = true; in tb_path_discover()
479 if (!path->activated) { in tb_path_deactivate()
491 path->activated = false; in tb_path_deactivate()
507 if (path->activated) { in tb_path_activate()
582 path->activated = true; in tb_path_activate()
/openbmc/phosphor-state-manager/target_files/
H A Dobmc-host-diagnostic-mode@.target2 # This target is activated when the host is
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_crc.c94 was_activated = acrtc->dm_irq_params.window_param.activated; in amdgpu_dm_set_crc_window_default()
99 acrtc->dm_irq_params.window_param.activated = false; in amdgpu_dm_set_crc_window_default()
189 ret = acrtc->dm_irq_params.window_param.activated; in amdgpu_dm_crc_window_is_activated()
490 if (!acrtc->dm_irq_params.window_param.activated) in amdgpu_dm_crtc_handle_crc_window_irq()
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_events.c42 bool activated; /* Becomes true when event is signaled */ member
640 WRITE_ONCE(waiter->activated, true); in set_event()
809 waiter->activated = ev->signaled; in init_event_waiter()
817 waiter->activated = true; in init_event_waiter()
820 if (!waiter->activated) in init_event_waiter()
847 if (READ_ONCE(event_waiters[i].activated)) { in test_event_condition()
878 if (waiter->activated) { in copy_signaled_event_data()
925 if (undo_auto_reset && waiters[i].activated && in free_waiters()
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dcn9131-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9130-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9132-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9130-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
/openbmc/u-boot/doc/
H A DREADME.VSC3316-330816 …n is 0x02 for two-wire interface. Also for crosspoint connections to be activated, 01.h value need…
41 …For crosspoint connections to be activated, 01.h value need to be written in 75.h (core configurat…
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Software/
H A DApplyTime.interface.yaml15 software image will be activated.

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