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/openbmc/u-boot/board/freescale/m54418twr/
H A Dsbf_dram_init.S12 move.l #0xFC04002D, %a1
13 move.b #46, (%a1) /* DDR */
16 move.l #0xEC094060, %a1
17 move.b #0, (%a1)
20 move.l #0xEC09001A, %a1
21 move.w #0xE01D, (%a1)
24 move.l #0xFC0B8180, %a1
25 move.l #0x00000000, (%a1)
26 move.l #0x40000000, (%a1)
28 move.l #0xFC0B81AC, %a1
[all …]
/openbmc/u-boot/board/sysam/stmark2/
H A Dsbf_dram_init.S25 move.l #PPMCR0, %a1
26 move.b #46, (%a1)
29 move.l #MSCR_SDRAMC, %a1
30 move.b #1, (%a1)
48 move.l #MISCCR2, %a1
49 move.w #0xa01d, (%a1)
52 move.l #DDR_RCR, %a1
53 move.l #0x00000000, (%a1)
54 move.l #0x40000000, (%a1)
60 move.l #DDR_PADCR, %a1
[all …]
/openbmc/qemu/include/fpu/
H A Dsoftfloat-macros.h190 uint64_t a0, uint64_t a1, int count, uint64_t *z0Ptr, uint64_t *z1Ptr) in shift64ExtraRightJamming() argument
196 z1 = a1; in shift64ExtraRightJamming()
200 z1 = ( a0<<negCount ) | ( a1 != 0 ); in shift64ExtraRightJamming()
205 z1 = a0 | ( a1 != 0 ); in shift64ExtraRightJamming()
208 z1 = ( ( a0 | a1 ) != 0 ); in shift64ExtraRightJamming()
227 uint64_t a0, uint64_t a1, int count, uint64_t *z0Ptr, uint64_t *z1Ptr) in shift128Right() argument
233 z1 = a1; in shift128Right()
237 z1 = ( a0<<negCount ) | ( a1>>count ); in shift128Right()
262 uint64_t a0, uint64_t a1, int count, uint64_t *z0Ptr, uint64_t *z1Ptr) in shift128RightJamming() argument
268 z1 = a1; in shift128RightJamming()
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dstart.S144 move.l #(ICACHE_STATUS), %a1 /* icache */
146 move.l %d0, (%a1)
163 move.l #0xFC008000, %a1
164 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
165 move.l #0xFC008008, %a1
166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
167 move.l #0xFC008004, %a1
168 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
175 move.l #0xFC04002D, %a1
178 move.b #23, (%a1) /* dspi */
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_mmu.S52 rdtlb0 a1, a3
55 assert eq, a1, a3
58 rdtlb1 a1, a3
61 assert eq, a1, a3
64 pdtlb a1, a3
67 assert eq, a1, a3
74 pdtlb a1, a3
77 and a1, a1, a3
78 assert eqi, a1, 0
155 movi a1, 1b
[all …]
H A Dtest_s32c1i.S15 movi a1, 2
16 s32c1i a1, a2, 0
17 assert ne, a1, a3
18 l32i a1, a2, 0
19 assert eqi, a1, 3
36 movi a1, 2
37 s32c1i a1, a2, 0
38 assert eq, a1, a3
39 l32i a1, a2, 0
40 assert eqi, a1, 2
/openbmc/u-boot/arch/m68k/cpu/mcf523x/
H A Dstart.S111 move.l #(ICACHE_STATUS), %a1 /* icache */
113 move.l %d0, (%a1)
127 move.l #board_init_f_alloc_reserve, %a1
128 jsr (%a1)
136 move.l #board_init_f_init_reserve, %a1
137 jsr (%a1)
140 move.l #cpu_init_f, %a1
141 jsr (%a1)
145 move.l #board_init_f, %a1
146 jsr (%a1)
[all …]
/openbmc/u-boot/arch/xtensa/cpu/
H A Dstart.S292 mov a1, a2
382 addi a1, a1, -16 - 4 # create a small stack frame
383 s32i a3, a1, 0 # and save a3 (a2 still in excsave1)
391 1: addi a2, a1, - PT_SIZE - 16
393 s32i a1, a2, PT_AREG + 1 * 4
397 mov a1, a2
401 s32i a4, a1, PT_AREG + 4 * 4
402 s32i a5, a1, PT_AREG + 5 * 4
403 s32i a6, a1, PT_AREG + 6 * 4
404 s32i a7, a1, PT_AREG + 7 * 4
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dstart.S115 move.l #0xFC008000, %a1
116 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
117 move.l #0xFC008008, %a1
118 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
119 move.l #0xFC008004, %a1
120 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
126 move.l #0xFC0A4074, %a1
127 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
131 move.l #0xFC0B8110, %a1
148 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dstart.S126 move.l #(ICACHE_STATUS), %a1 /* icache */
128 move.l %d0, (%a1)
142 move.l #board_init_f_alloc_reserve, %a1
143 jsr (%a1)
151 move.l #board_init_f_init_reserve, %a1
152 jsr (%a1)
155 move.l #cpu_init_f, %a1
156 jsr (%a1)
160 move.l #board_init_f, %a1
161 jsr (%a1)
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dstart.S140 move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
144 cmp.l %a0, %a1
190 move.l #(ICACHE_STATUS), %a1 /* icache */
192 move.l %d0, (%a1)
206 move.l #board_init_f_alloc_reserve, %a1
207 jsr (%a1)
215 move.l #board_init_f_init_reserve, %a1
216 jsr (%a1)
219 move.l #cpu_init_f, %a1
220 jsr (%a1)
[all …]
/openbmc/u-boot/board/freescale/m54455evb/
H A Dsbf_dram_init.S16 move.l #0xFC0A4074, %a1
17 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
21 move.l #0xFC0B8110, %a1
40 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
41 or.l %d1, (%a1)
49 move.l #0xFC0B8008, %a1
50 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
56 move.l #0xFC0B8000, %a1 /* Mode */
64 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
66 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
[all …]
/openbmc/u-boot/board/freescale/m54451evb/
H A Dsbf_dram_init.S16 move.l #0xFC0A4074, %a1
17 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
21 move.l #0xFC0B8110, %a1
40 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
41 or.l %d1, (%a1)
49 move.l #0xFC0B8008, %a1
50 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
56 move.l #0xFC0B8000, %a1 /* Mode */
78 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
80 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
/openbmc/u-boot/arch/arm/lib/
H A Dsetjmp.S18 stm a1, {v1-v8, ip, lr}
19 mov a1, #0
26 ldm a1, {v1-v8, ip, lr}
28 mov a1, a2
30 cmp a1, #0
32 mov a1, #1
/openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/
H A Dstart.S118 move.l #(ICACHE_STATUS), %a1 /* icache */
120 move.l %d0, (%a1)
174 move.l #CONFIG_SYS_MONITOR_BASE, %a1
180 move.l (%a1)+, (%a3)+
181 cmp.l %a1,%a2
188 move.l %a0, %a1
189 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
190 jmp (%a1)
198 move.l %a0, %a1
199 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf530x/
H A Dstart.S120 move.l #(ICACHE_STATUS), %a1 /* icache */
122 move.l %d0, (%a1)
171 move.l #CONFIG_SYS_MONITOR_BASE, %a1
176 move.l (%a1)+, (%a3)+
177 cmp.l %a1,%a2
184 move.l %a0, %a1
185 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
186 jmp (%a1)
194 move.l %a0, %a1
195 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dcc_helper.c136 static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, int64_t ar) in cc_calc_add_64() argument
138 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar >= 0)) { in cc_calc_add_64()
151 static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2, int64_t ar) in cc_calc_sub_64() argument
153 if ((a1 >= 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { in cc_calc_sub_64()
196 static uint32_t cc_calc_add_32(int32_t a1, int32_t a2, int32_t ar) in cc_calc_add_32() argument
198 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar >= 0)) { in cc_calc_add_32()
211 static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2, int32_t ar) in cc_calc_sub_32() argument
213 if ((a1 >= 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { in cc_calc_sub_32()
485 void HELPER(sacf)(CPUS390XState *env, uint64_t a1) in HELPER()
487 HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1); in HELPER()
[all …]
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc493 TCGReg a0, TCGReg a1, TCGReg a2)
495 tcg_out_op_rrr(s, INDEX_op_add, a0, a1, a2);
509 TCGReg a0, TCGReg a1, TCGReg a2)
511 tcg_out_op_rrr(s, INDEX_op_addco, a0, a1, a2);
521 TCGReg a0, TCGReg a1, TCGReg a2)
523 tcg_out_op_rrr(s, INDEX_op_addci, a0, a1, a2);
533 TCGReg a0, TCGReg a1, TCGReg a2)
535 tcg_out_op_rrr(s, INDEX_op_addcio, a0, a1, a2);
550 TCGReg a0, TCGReg a1, TCGReg a2)
552 tcg_out_op_rrr(s, INDEX_op_and, a0, a1, a2);
[all …]
/openbmc/u-boot/cmd/
H A Dsmccc.c19 unsigned long a1; in do_call() local
32 a1 = argc > 2 ? simple_strtoul(argv[2], NULL, 16) : 0; in do_call()
41 arm_smccc_smc(fid, a1, a2, a3, a4, a5, a6, a7, &res); in do_call()
43 arm_smccc_hvc(fid, a1, a2, a3, a4, a5, a6, a7, &res); in do_call()
45 printf("Res: %ld %ld %ld %ld\n", res.a0, res.a1, res.a2, res.a3); in do_call()
/openbmc/u-boot/fs/zfs/
H A Dzfs_fletcher.c40 uint64_t a0, b0, a1, b1; in fletcher_2_endian() local
42 for (a0 = b0 = a1 = b1 = 0; ip < ipend; ip += 2) { in fletcher_2_endian()
44 a1 += zfs_to_cpu64(ip[1], endian); in fletcher_2_endian()
46 b1 += a1; in fletcher_2_endian()
50 zcp->zc_word[1] = cpu_to_zfs64(a1, endian); in fletcher_2_endian()
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc2045 TCGReg a0, TCGReg a1, TCGReg a2)
2047 tcg_out_insn(s, 3502, ADD, type, a0, a1, a2);
2051 TCGReg a0, TCGReg a1, tcg_target_long a2)
2054 tcg_out_insn(s, 3401, ADDI, type, a0, a1, a2);
2056 tcg_out_insn(s, 3401, SUBI, type, a0, a1, -a2);
2067 TCGReg a0, TCGReg a1, TCGReg a2)
2069 tcg_out_insn(s, 3502, ADDS, type, a0, a1, a2);
2073 TCGReg a0, TCGReg a1, tcg_target_long a2)
2076 tcg_out_insn(s, 3401, ADDSI, type, a0, a1, a2);
2078 tcg_out_insn(s, 3401, SUBSI, type, a0, a1, -a2);
[all …]
/openbmc/webui-vue/src/assets/images/
H A Dlogo-header.svg1 …a1.61 1.61 0 011.834-1.707c2.157-2.655 3.036-6.877 1.246-10.714-1.976-4.235-5.944-5.847-8.593-5.99…
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc50 "a1",
1369 TCGReg a0, TCGReg a1, TCGReg a2)
1372 tcg_out_opc_add_w(s, a0, a1, a2);
1374 tcg_out_opc_add_d(s, a0, a1, a2);
1402 TCGReg a0, TCGReg a1, TCGReg a2)
1404 tcg_out_opc_and(s, a0, a1, a2);
1408 TCGReg a0, TCGReg a1, tcg_target_long a2)
1410 tcg_out_opc_andi(s, a0, a1, a2);
1420 TCGReg a0, TCGReg a1, TCGReg a2)
1422 tcg_out_opc_andn(s, a0, a1, a2);
[all …]
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc562 static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
565 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
1338 TCGReg a0, TCGReg a1, TCGReg a2)
1340 tcg_out_arith(s, a0, a1, a2, ARITH_ADD);
1344 TCGReg a0, TCGReg a1, tcg_target_long a2)
1346 tcg_out_arithi(s, a0, a1, a2, ARITH_ADD);
1356 TCGReg a0, TCGReg a1, TCGReg a2)
1358 tcg_out_arith(s, a0, a1, a2, ARITH_ADDCC);
1362 TCGReg a0, TCGReg a1, tcg_target_long a2)
1364 tcg_out_arithi(s, a0, a1, a2, ARITH_ADDCC);
[all …]
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc1582 static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
1589 * Since we can't support "0Z" as a constraint, we allow a1 in
1592 if (a0 != a1) {
1597 tcg_out_mov(s, type, a0, a1);
1771 TCGReg a0, TCGReg a1, TCGLabel *l)
1773 tgen_brcond(s, type, c, a0, a1, false, l);
1777 TCGReg a0, tcg_target_long a1, TCGLabel *l)
1779 tgen_brcond(s, type, c, a0, a1, true, l);
2268 TCGReg a0, TCGReg a1, TCGReg a2)
2270 if (a0 != a1) {
[all …]

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