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Searched refs:_pd_reg (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7981-apmixed.c26 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ argument
32 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
41 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
H A Dclk-mt7986-apmixed.c24 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ argument
30 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
39 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
H A Dclk-mt8516-apmixedsys.c24 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
35 .pd_reg = _pd_reg, \
44 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
47 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8167-apmixedsys.c23 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
34 .pd_reg = _pd_reg, \
43 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
46 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt7622-apmixedsys.c21 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
32 .pd_reg = _pd_reg, \
42 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
45 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt2712-apmixedsys.c22 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ argument
34 .pd_reg = _pd_reg, \
45 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ argument
48 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
H A Dclk-mt8365-apmixedsys.c20 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ argument
34 .pd_reg = _pd_reg, \
46 _pd_reg, _pd_shift, _tuner_reg, \ argument
50 _pcwbits, _pd_reg, _pd_shift, \
H A Dclk-mt8183-apmixedsys.c55 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
70 .pd_reg = _pd_reg, \
82 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
87 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
H A Dclk-mt8173-apmixedsys.c25 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
36 .pd_reg = _pd_reg, \
45 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
48 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8192-apmixedsys.c36 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
51 .pd_reg = _pd_reg, \
64 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
68 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
H A Dclk-mt8195-apusys_pll.c28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ argument
40 .pd_reg = _pd_reg, \
H A Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
30 .pd_reg = _pd_reg, \
H A Dclk-mt8188-apmixedsys.c33 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
48 .pd_reg = _pd_reg, \
H A Dclk-mt7629.c24 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
35 .pd_reg = _pd_reg, \
45 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
48 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt6797.c600 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
611 .pd_reg = _pd_reg, \
620 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ argument
623 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8186-apmixedsys.c20 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
34 .pd_reg = _pd_reg, \
H A Dclk-mt8195-apmixedsys.c34 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
49 .pd_reg = _pd_reg, \
H A Dclk-mt6795-apmixedsys.c27 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ argument
37 .pd_reg = _pd_reg, \
H A Dclk-mt6765.c672 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\ argument
685 .pd_reg = _pd_reg, \
696 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \ argument
700 _pcwbits, _pcwibits, _pd_reg, _pd_shift, \
H A Dclk-mt6779.c1146 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
1161 .pd_reg = _pd_reg, \
1173 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
1178 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
H A Dclk-mt2701.c921 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
932 .pd_reg = _pd_reg, \
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
41 .pd_reg = _pd_reg, \
H A Dclk-mt7623.c27 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
37 .pd_reg = _pd_reg, \