Searched refs:XIIC_INTR_TX_ERROR_MASK (Results 1 – 2 of 2) sorted by relevance
63 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ macro165 xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK); in xilinx_xiic_set_addr()186 xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); in xilinx_xiic_read_common()229 xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | in xilinx_xiic_write_common()299 if (reg & XIIC_INTR_TX_ERROR_MASK) in xilinx_xiic_probe_chip()
180 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ macro196 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)698 ((pend & XIIC_INTR_TX_ERROR_MASK) && in xiic_process()744 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); in xiic_process()896 XIIC_INTR_TX_ERROR_MASK); in xiic_start_recv()971 XIIC_INTR_TX_ERROR_MASK); in xiic_start_recv()1026 XIIC_INTR_TX_ERROR_MASK | in xiic_start_send()1073 XIIC_INTR_TX_ERROR_MASK | in xiic_start_send()