Searched refs:XIIC_INTR_TX_EMPTY_MASK (Results 1 – 2 of 2) sorted by relevance
181 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ macro196 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)348 !(isr & XIIC_INTR_TX_EMPTY_MASK); in xiic_wait_tx_empty()763 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { in xiic_process()767 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); in xiic_process()785 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) { in xiic_process()875 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); in xiic_start_recv()1012 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()1059 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()
64 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ macro229 xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | in xilinx_xiic_write_common()