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Searched refs:WR_LVL_PH_SEL_OFFS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h390 #define WR_LVL_PH_SEL_OFFS 6 macro
H A Dddr3_training_leveling.c1074 temp = (reg_data >> WR_LVL_PH_SEL_OFFS) & WR_LVL_PH_SEL_PHASE1; in ddr3_tip_dynamic_write_leveling()
1075 reg_data &= ~(WR_LVL_PH_SEL_MASK << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling()
1076 reg_data |= (temp << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling()