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Searched refs:WR_CONFIRM (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnvd.h98 #define WR_CONFIRM (1 << 20) macro
H A Dsoc15d.h125 #define WR_CONFIRM (1 << 20) macro
H A Dvid.h151 #define WR_CONFIRM (1 << 20) macro
H A Dcikd.h269 #define WR_CONFIRM (1 << 20) macro
H A Dgfx_v9_4_3.c219 (wc ? WR_CONFIRM : 0)); in gfx_v9_4_3_write_data_to_reg()
305 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()
2634 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
2643 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
2674 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
2680 cmd = WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
H A Dgfx_v9_0.c966 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()
1048 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
5397 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5406 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5446 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()
5559 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()
5664 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
5670 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
H A Dgfx_v11_0.c293 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
409 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()
5445 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5454 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5616 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()
5662 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
5668 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
H A Dgfx_v8_0.c892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
6275 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6284 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6381 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
6387 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
7192 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()
7225 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
H A Dgfx_v10_0.c3738 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()
3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()
8446 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8455 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8604 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()
8655 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()
8701 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
8707 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
H A Dsid.h1709 #define WR_CONFIRM (1 << 20) macro
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsid.h1646 #define WR_CONFIRM (1 << 20) macro
H A Dcikd.h1737 #define WR_CONFIRM (1 << 20) macro