198cd7f5bSHawking Zhang /* 298cd7f5bSHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 398cd7f5bSHawking Zhang * 498cd7f5bSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 598cd7f5bSHawking Zhang * copy of this software and associated documentation files (the "Software"), 698cd7f5bSHawking Zhang * to deal in the Software without restriction, including without limitation 798cd7f5bSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 898cd7f5bSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 998cd7f5bSHawking Zhang * Software is furnished to do so, subject to the following conditions: 1098cd7f5bSHawking Zhang * 1198cd7f5bSHawking Zhang * The above copyright notice and this permission notice shall be included in 1298cd7f5bSHawking Zhang * all copies or substantial portions of the Software. 1398cd7f5bSHawking Zhang * 1498cd7f5bSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1598cd7f5bSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1698cd7f5bSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1798cd7f5bSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1898cd7f5bSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1998cd7f5bSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2098cd7f5bSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 2198cd7f5bSHawking Zhang * 2298cd7f5bSHawking Zhang */ 2398cd7f5bSHawking Zhang 2498cd7f5bSHawking Zhang #ifndef NVD_H 2598cd7f5bSHawking Zhang #define NVD_H 2698cd7f5bSHawking Zhang 2798cd7f5bSHawking Zhang /** 2898cd7f5bSHawking Zhang * Navi's PM4 definitions 2998cd7f5bSHawking Zhang */ 3098cd7f5bSHawking Zhang #define PACKET_TYPE0 0 3198cd7f5bSHawking Zhang #define PACKET_TYPE1 1 3298cd7f5bSHawking Zhang #define PACKET_TYPE2 2 3398cd7f5bSHawking Zhang #define PACKET_TYPE3 3 3498cd7f5bSHawking Zhang 3598cd7f5bSHawking Zhang #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 3698cd7f5bSHawking Zhang #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 3798cd7f5bSHawking Zhang #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 3898cd7f5bSHawking Zhang #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 3998cd7f5bSHawking Zhang #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 4098cd7f5bSHawking Zhang ((reg) & 0xFFFF) | \ 4198cd7f5bSHawking Zhang ((n) & 0x3FFF) << 16) 4298cd7f5bSHawking Zhang #define CP_PACKET2 0x80000000 4398cd7f5bSHawking Zhang #define PACKET2_PAD_SHIFT 0 4498cd7f5bSHawking Zhang #define PACKET2_PAD_MASK (0x3fffffff << 0) 4598cd7f5bSHawking Zhang 4698cd7f5bSHawking Zhang #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 4798cd7f5bSHawking Zhang 4898cd7f5bSHawking Zhang #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 4998cd7f5bSHawking Zhang (((op) & 0xFF) << 8) | \ 5098cd7f5bSHawking Zhang ((n) & 0x3FFF) << 16) 5198cd7f5bSHawking Zhang 5298cd7f5bSHawking Zhang #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 5398cd7f5bSHawking Zhang 5498cd7f5bSHawking Zhang /* Packet 3 types */ 5598cd7f5bSHawking Zhang #define PACKET3_NOP 0x10 5698cd7f5bSHawking Zhang #define PACKET3_SET_BASE 0x11 5798cd7f5bSHawking Zhang #define PACKET3_BASE_INDEX(x) ((x) << 0) 5898cd7f5bSHawking Zhang #define CE_PARTITION_BASE 3 5998cd7f5bSHawking Zhang #define PACKET3_CLEAR_STATE 0x12 6098cd7f5bSHawking Zhang #define PACKET3_INDEX_BUFFER_SIZE 0x13 6198cd7f5bSHawking Zhang #define PACKET3_DISPATCH_DIRECT 0x15 6298cd7f5bSHawking Zhang #define PACKET3_DISPATCH_INDIRECT 0x16 6398cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER_END 0x17 6498cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 6598cd7f5bSHawking Zhang #define PACKET3_ATOMIC_GDS 0x1D 6698cd7f5bSHawking Zhang #define PACKET3_ATOMIC_MEM 0x1E 6798cd7f5bSHawking Zhang #define PACKET3_OCCLUSION_QUERY 0x1F 6898cd7f5bSHawking Zhang #define PACKET3_SET_PREDICATION 0x20 6998cd7f5bSHawking Zhang #define PACKET3_REG_RMW 0x21 7098cd7f5bSHawking Zhang #define PACKET3_COND_EXEC 0x22 7198cd7f5bSHawking Zhang #define PACKET3_PRED_EXEC 0x23 7298cd7f5bSHawking Zhang #define PACKET3_DRAW_INDIRECT 0x24 7398cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_INDIRECT 0x25 7498cd7f5bSHawking Zhang #define PACKET3_INDEX_BASE 0x26 7598cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_2 0x27 7698cd7f5bSHawking Zhang #define PACKET3_CONTEXT_CONTROL 0x28 7798cd7f5bSHawking Zhang #define PACKET3_INDEX_TYPE 0x2A 7898cd7f5bSHawking Zhang #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 7998cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_AUTO 0x2D 8098cd7f5bSHawking Zhang #define PACKET3_NUM_INSTANCES 0x2F 8198cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 8298cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER_PRIV 0x32 8398cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER_CNST 0x33 8498cd7f5bSHawking Zhang #define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 8598cd7f5bSHawking Zhang #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 8698cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 8798cd7f5bSHawking Zhang #define PACKET3_DRAW_PREAMBLE 0x36 8898cd7f5bSHawking Zhang #define PACKET3_WRITE_DATA 0x37 8998cd7f5bSHawking Zhang #define WRITE_DATA_DST_SEL(x) ((x) << 8) 9098cd7f5bSHawking Zhang /* 0 - register 9198cd7f5bSHawking Zhang * 1 - memory (sync - via GRBM) 9298cd7f5bSHawking Zhang * 2 - gl2 9398cd7f5bSHawking Zhang * 3 - gds 9498cd7f5bSHawking Zhang * 4 - reserved 9598cd7f5bSHawking Zhang * 5 - memory (async - direct) 9698cd7f5bSHawking Zhang */ 9798cd7f5bSHawking Zhang #define WR_ONE_ADDR (1 << 16) 9898cd7f5bSHawking Zhang #define WR_CONFIRM (1 << 20) 9998cd7f5bSHawking Zhang #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 10098cd7f5bSHawking Zhang /* 0 - LRU 10198cd7f5bSHawking Zhang * 1 - Stream 10298cd7f5bSHawking Zhang */ 10398cd7f5bSHawking Zhang #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 10498cd7f5bSHawking Zhang /* 0 - me 10598cd7f5bSHawking Zhang * 1 - pfp 10698cd7f5bSHawking Zhang * 2 - ce 10798cd7f5bSHawking Zhang */ 10898cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 10998cd7f5bSHawking Zhang #define PACKET3_MEM_SEMAPHORE 0x39 11098cd7f5bSHawking Zhang # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 11198cd7f5bSHawking Zhang # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 11298cd7f5bSHawking Zhang # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 11398cd7f5bSHawking Zhang # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 11498cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_MULTI_INST 0x3A 11598cd7f5bSHawking Zhang #define PACKET3_COPY_DW 0x3B 11698cd7f5bSHawking Zhang #define PACKET3_WAIT_REG_MEM 0x3C 11798cd7f5bSHawking Zhang #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 11898cd7f5bSHawking Zhang /* 0 - always 11998cd7f5bSHawking Zhang * 1 - < 12098cd7f5bSHawking Zhang * 2 - <= 12198cd7f5bSHawking Zhang * 3 - == 12298cd7f5bSHawking Zhang * 4 - != 12398cd7f5bSHawking Zhang * 5 - >= 12498cd7f5bSHawking Zhang * 6 - > 12598cd7f5bSHawking Zhang */ 12698cd7f5bSHawking Zhang #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 12798cd7f5bSHawking Zhang /* 0 - reg 12898cd7f5bSHawking Zhang * 1 - mem 12998cd7f5bSHawking Zhang */ 13098cd7f5bSHawking Zhang #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 13198cd7f5bSHawking Zhang /* 0 - wait_reg_mem 13298cd7f5bSHawking Zhang * 1 - wr_wait_wr_reg 13398cd7f5bSHawking Zhang */ 13498cd7f5bSHawking Zhang #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 13598cd7f5bSHawking Zhang /* 0 - me 13698cd7f5bSHawking Zhang * 1 - pfp 13798cd7f5bSHawking Zhang */ 13898cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER 0x3F 13998cd7f5bSHawking Zhang #define INDIRECT_BUFFER_VALID (1 << 23) 14098cd7f5bSHawking Zhang #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 14198cd7f5bSHawking Zhang /* 0 - LRU 14298cd7f5bSHawking Zhang * 1 - Stream 14398cd7f5bSHawking Zhang * 2 - Bypass 14498cd7f5bSHawking Zhang */ 14598cd7f5bSHawking Zhang #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 14698cd7f5bSHawking Zhang #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) 14798cd7f5bSHawking Zhang #define PACKET3_COND_INDIRECT_BUFFER 0x3F 14898cd7f5bSHawking Zhang #define PACKET3_COPY_DATA 0x40 14998cd7f5bSHawking Zhang #define PACKET3_CP_DMA 0x41 15098cd7f5bSHawking Zhang #define PACKET3_PFP_SYNC_ME 0x42 15198cd7f5bSHawking Zhang #define PACKET3_SURFACE_SYNC 0x43 15298cd7f5bSHawking Zhang #define PACKET3_ME_INITIALIZE 0x44 15398cd7f5bSHawking Zhang #define PACKET3_COND_WRITE 0x45 15498cd7f5bSHawking Zhang #define PACKET3_EVENT_WRITE 0x46 15598cd7f5bSHawking Zhang #define EVENT_TYPE(x) ((x) << 0) 15698cd7f5bSHawking Zhang #define EVENT_INDEX(x) ((x) << 8) 15798cd7f5bSHawking Zhang /* 0 - any non-TS event 15898cd7f5bSHawking Zhang * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 15998cd7f5bSHawking Zhang * 2 - SAMPLE_PIPELINESTAT 16098cd7f5bSHawking Zhang * 3 - SAMPLE_STREAMOUTSTAT* 16198cd7f5bSHawking Zhang * 4 - *S_PARTIAL_FLUSH 16298cd7f5bSHawking Zhang */ 16398cd7f5bSHawking Zhang #define PACKET3_EVENT_WRITE_EOP 0x47 16498cd7f5bSHawking Zhang #define PACKET3_EVENT_WRITE_EOS 0x48 16598cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM 0x49 16698cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 16798cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) 16898cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12) 16998cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13) 17098cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) 17198cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15) 17298cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) 17398cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17) 17498cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) 17598cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) 17698cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) 17798cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22) 17898cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) 17998cd7f5bSHawking Zhang /* 0 - cache_policy__me_release_mem__lru 18098cd7f5bSHawking Zhang * 1 - cache_policy__me_release_mem__stream 18198cd7f5bSHawking Zhang * 2 - cache_policy__me_release_mem__noa 18298cd7f5bSHawking Zhang * 3 - cache_policy__me_release_mem__bypass 18398cd7f5bSHawking Zhang */ 18498cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) 18598cd7f5bSHawking Zhang 18698cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 18798cd7f5bSHawking Zhang /* 0 - discard 18898cd7f5bSHawking Zhang * 1 - send low 32bit data 18998cd7f5bSHawking Zhang * 2 - send 64bit data 19098cd7f5bSHawking Zhang * 3 - send 64bit GPU counter value 19198cd7f5bSHawking Zhang * 4 - send 64bit sys counter value 19298cd7f5bSHawking Zhang */ 19398cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 19498cd7f5bSHawking Zhang /* 0 - none 19598cd7f5bSHawking Zhang * 1 - interrupt only (DATA_SEL = 0) 19698cd7f5bSHawking Zhang * 2 - interrupt when data write is confirmed 19798cd7f5bSHawking Zhang */ 19898cd7f5bSHawking Zhang #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 19998cd7f5bSHawking Zhang /* 0 - MC 20098cd7f5bSHawking Zhang * 1 - TC/L2 20198cd7f5bSHawking Zhang */ 20298cd7f5bSHawking Zhang 20398cd7f5bSHawking Zhang 20498cd7f5bSHawking Zhang 20598cd7f5bSHawking Zhang #define PACKET3_PREAMBLE_CNTL 0x4A 20698cd7f5bSHawking Zhang # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 20798cd7f5bSHawking Zhang # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 20898cd7f5bSHawking Zhang #define PACKET3_DMA_DATA 0x50 20998cd7f5bSHawking Zhang /* 1. header 21098cd7f5bSHawking Zhang * 2. CONTROL 21198cd7f5bSHawking Zhang * 3. SRC_ADDR_LO or DATA [31:0] 21298cd7f5bSHawking Zhang * 4. SRC_ADDR_HI [31:0] 21398cd7f5bSHawking Zhang * 5. DST_ADDR_LO [31:0] 21498cd7f5bSHawking Zhang * 6. DST_ADDR_HI [7:0] 21598cd7f5bSHawking Zhang * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 21698cd7f5bSHawking Zhang */ 21798cd7f5bSHawking Zhang /* CONTROL */ 21898cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 21998cd7f5bSHawking Zhang /* 0 - ME 22098cd7f5bSHawking Zhang * 1 - PFP 22198cd7f5bSHawking Zhang */ 22298cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 22398cd7f5bSHawking Zhang /* 0 - LRU 22498cd7f5bSHawking Zhang * 1 - Stream 22598cd7f5bSHawking Zhang */ 22698cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 22798cd7f5bSHawking Zhang /* 0 - DST_ADDR using DAS 22898cd7f5bSHawking Zhang * 1 - GDS 22998cd7f5bSHawking Zhang * 3 - DST_ADDR using L2 23098cd7f5bSHawking Zhang */ 23198cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 23298cd7f5bSHawking Zhang /* 0 - LRU 23398cd7f5bSHawking Zhang * 1 - Stream 23498cd7f5bSHawking Zhang */ 23598cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 23698cd7f5bSHawking Zhang /* 0 - SRC_ADDR using SAS 23798cd7f5bSHawking Zhang * 1 - GDS 23898cd7f5bSHawking Zhang * 2 - DATA 23998cd7f5bSHawking Zhang * 3 - SRC_ADDR using L2 24098cd7f5bSHawking Zhang */ 24198cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 24298cd7f5bSHawking Zhang /* COMMAND */ 24398cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 24498cd7f5bSHawking Zhang /* 0 - memory 24598cd7f5bSHawking Zhang * 1 - register 24698cd7f5bSHawking Zhang */ 24798cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 24898cd7f5bSHawking Zhang /* 0 - memory 24998cd7f5bSHawking Zhang * 1 - register 25098cd7f5bSHawking Zhang */ 25198cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 25298cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 25398cd7f5bSHawking Zhang # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 25498cd7f5bSHawking Zhang #define PACKET3_CONTEXT_REG_RMW 0x51 25598cd7f5bSHawking Zhang #define PACKET3_GFX_CNTX_UPDATE 0x52 25698cd7f5bSHawking Zhang #define PACKET3_BLK_CNTX_UPDATE 0x53 25798cd7f5bSHawking Zhang #define PACKET3_INCR_UPDT_STATE 0x55 25898cd7f5bSHawking Zhang #define PACKET3_ACQUIRE_MEM 0x58 25973339a71SAndrey Grodzovsky /* 1. HEADER 26073339a71SAndrey Grodzovsky * 2. COHER_CNTL [30:0] 26173339a71SAndrey Grodzovsky * 2.1 ENGINE_SEL [31:31] 26273339a71SAndrey Grodzovsky * 2. COHER_SIZE [31:0] 26373339a71SAndrey Grodzovsky * 3. COHER_SIZE_HI [7:0] 26473339a71SAndrey Grodzovsky * 4. COHER_BASE_LO [31:0] 26573339a71SAndrey Grodzovsky * 5. COHER_BASE_HI [23:0] 26673339a71SAndrey Grodzovsky * 7. POLL_INTERVAL [15:0] 26773339a71SAndrey Grodzovsky * 8. GCR_CNTL [18:0] 26873339a71SAndrey Grodzovsky */ 26973339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) 27073339a71SAndrey Grodzovsky /* 27173339a71SAndrey Grodzovsky * 0:NOP 27273339a71SAndrey Grodzovsky * 1:ALL 27373339a71SAndrey Grodzovsky * 2:RANGE 27473339a71SAndrey Grodzovsky * 3:FIRST_LAST 27573339a71SAndrey Grodzovsky */ 27673339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) 27773339a71SAndrey Grodzovsky /* 27873339a71SAndrey Grodzovsky * 0:ALL 27973339a71SAndrey Grodzovsky * 1:reserved 28073339a71SAndrey Grodzovsky * 2:RANGE 28173339a71SAndrey Grodzovsky * 3:FIRST_LAST 28273339a71SAndrey Grodzovsky */ 28373339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) 28473339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) 28573339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) 28673339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) 28773339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) 28873339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) 28973339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) 29073339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) 29173339a71SAndrey Grodzovsky /* 29273339a71SAndrey Grodzovsky * 0:ALL 29373339a71SAndrey Grodzovsky * 1:VOL 29473339a71SAndrey Grodzovsky * 2:RANGE 29573339a71SAndrey Grodzovsky * 3:FIRST_LAST 29673339a71SAndrey Grodzovsky */ 29773339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) 29873339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) 29973339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) 30073339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) 30173339a71SAndrey Grodzovsky /* 30273339a71SAndrey Grodzovsky * 0: PARALLEL 30373339a71SAndrey Grodzovsky * 1: FORWARD 30473339a71SAndrey Grodzovsky * 2: REVERSE 30573339a71SAndrey Grodzovsky */ 30673339a71SAndrey Grodzovsky #define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) 30798cd7f5bSHawking Zhang #define PACKET3_REWIND 0x59 30898cd7f5bSHawking Zhang #define PACKET3_INTERRUPT 0x5A 30998cd7f5bSHawking Zhang #define PACKET3_GEN_PDEPTE 0x5B 31098cd7f5bSHawking Zhang #define PACKET3_INDIRECT_BUFFER_PASID 0x5C 31198cd7f5bSHawking Zhang #define PACKET3_PRIME_UTCL2 0x5D 31298cd7f5bSHawking Zhang #define PACKET3_LOAD_UCONFIG_REG 0x5E 31398cd7f5bSHawking Zhang #define PACKET3_LOAD_SH_REG 0x5F 31498cd7f5bSHawking Zhang #define PACKET3_LOAD_CONFIG_REG 0x60 31598cd7f5bSHawking Zhang #define PACKET3_LOAD_CONTEXT_REG 0x61 31698cd7f5bSHawking Zhang #define PACKET3_LOAD_COMPUTE_STATE 0x62 31798cd7f5bSHawking Zhang #define PACKET3_LOAD_SH_REG_INDEX 0x63 31898cd7f5bSHawking Zhang #define PACKET3_SET_CONFIG_REG 0x68 31998cd7f5bSHawking Zhang #define PACKET3_SET_CONFIG_REG_START 0x00002000 32098cd7f5bSHawking Zhang #define PACKET3_SET_CONFIG_REG_END 0x00002c00 32198cd7f5bSHawking Zhang #define PACKET3_SET_CONTEXT_REG 0x69 32298cd7f5bSHawking Zhang #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 32398cd7f5bSHawking Zhang #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 32498cd7f5bSHawking Zhang #define PACKET3_SET_CONTEXT_REG_INDEX 0x6A 32598cd7f5bSHawking Zhang #define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 32698cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_DI 0x72 32798cd7f5bSHawking Zhang #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 32898cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_DI_MULTI 0x74 32998cd7f5bSHawking Zhang #define PACKET3_GFX_PIPE_LOCK 0x75 33098cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG 0x76 33198cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_START 0x00002c00 33298cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_END 0x00003000 33398cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_OFFSET 0x77 33498cd7f5bSHawking Zhang #define PACKET3_SET_QUEUE_REG 0x78 33598cd7f5bSHawking Zhang #define PACKET3_SET_UCONFIG_REG 0x79 33698cd7f5bSHawking Zhang #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 33798cd7f5bSHawking Zhang #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 33898cd7f5bSHawking Zhang #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 33998cd7f5bSHawking Zhang #define PACKET3_FORWARD_HEADER 0x7C 34098cd7f5bSHawking Zhang #define PACKET3_SCRATCH_RAM_WRITE 0x7D 34198cd7f5bSHawking Zhang #define PACKET3_SCRATCH_RAM_READ 0x7E 34298cd7f5bSHawking Zhang #define PACKET3_LOAD_CONST_RAM 0x80 34398cd7f5bSHawking Zhang #define PACKET3_WRITE_CONST_RAM 0x81 34498cd7f5bSHawking Zhang #define PACKET3_DUMP_CONST_RAM 0x83 34598cd7f5bSHawking Zhang #define PACKET3_INCREMENT_CE_COUNTER 0x84 34698cd7f5bSHawking Zhang #define PACKET3_INCREMENT_DE_COUNTER 0x85 34798cd7f5bSHawking Zhang #define PACKET3_WAIT_ON_CE_COUNTER 0x86 34898cd7f5bSHawking Zhang #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 34998cd7f5bSHawking Zhang #define PACKET3_SWITCH_BUFFER 0x8B 35098cd7f5bSHawking Zhang #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 35198cd7f5bSHawking Zhang #define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C 35298cd7f5bSHawking Zhang #define PACKET3_DISPATCH_DRAW 0x8D 35398cd7f5bSHawking Zhang #define PACKET3_DISPATCH_DRAW_ACE 0x8D 35498cd7f5bSHawking Zhang #define PACKET3_GET_LOD_STATS 0x8E 35598cd7f5bSHawking Zhang #define PACKET3_DRAW_MULTI_PREAMBLE 0x8F 35698cd7f5bSHawking Zhang #define PACKET3_FRAME_CONTROL 0x90 357eda982a6SHuang Rui # define FRAME_TMZ (1 << 0) 35898cd7f5bSHawking Zhang # define FRAME_CMD(x) ((x) << 28) 35998cd7f5bSHawking Zhang /* 36098cd7f5bSHawking Zhang * x=0: tmz_begin 36198cd7f5bSHawking Zhang * x=1: tmz_end 36298cd7f5bSHawking Zhang */ 36398cd7f5bSHawking Zhang #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 36498cd7f5bSHawking Zhang #define PACKET3_WAIT_REG_MEM64 0x93 36598cd7f5bSHawking Zhang #define PACKET3_COND_PREEMPT 0x94 36698cd7f5bSHawking Zhang #define PACKET3_HDP_FLUSH 0x95 36798cd7f5bSHawking Zhang #define PACKET3_COPY_DATA_RB 0x96 36898cd7f5bSHawking Zhang #define PACKET3_INVALIDATE_TLBS 0x98 36998cd7f5bSHawking Zhang # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 37098cd7f5bSHawking Zhang # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 37198cd7f5bSHawking Zhang # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 37298cd7f5bSHawking Zhang #define PACKET3_AQL_PACKET 0x99 37398cd7f5bSHawking Zhang #define PACKET3_DMA_DATA_FILL_MULTI 0x9A 37498cd7f5bSHawking Zhang #define PACKET3_SET_SH_REG_INDEX 0x9B 37598cd7f5bSHawking Zhang #define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C 37698cd7f5bSHawking Zhang #define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D 37798cd7f5bSHawking Zhang #define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E 37898cd7f5bSHawking Zhang #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 37998cd7f5bSHawking Zhang #define PACKET3_SET_RESOURCES 0xA0 38098cd7f5bSHawking Zhang /* 1. header 38198cd7f5bSHawking Zhang * 2. CONTROL 38298cd7f5bSHawking Zhang * 3. QUEUE_MASK_LO [31:0] 38398cd7f5bSHawking Zhang * 4. QUEUE_MASK_HI [31:0] 38498cd7f5bSHawking Zhang * 5. GWS_MASK_LO [31:0] 38598cd7f5bSHawking Zhang * 6. GWS_MASK_HI [31:0] 38698cd7f5bSHawking Zhang * 7. OAC_MASK [15:0] 38798cd7f5bSHawking Zhang * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 38898cd7f5bSHawking Zhang */ 38998cd7f5bSHawking Zhang # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 39098cd7f5bSHawking Zhang # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 39198cd7f5bSHawking Zhang # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 39298cd7f5bSHawking Zhang #define PACKET3_MAP_PROCESS 0xA1 39398cd7f5bSHawking Zhang #define PACKET3_MAP_QUEUES 0xA2 39498cd7f5bSHawking Zhang /* 1. header 39598cd7f5bSHawking Zhang * 2. CONTROL 39698cd7f5bSHawking Zhang * 3. CONTROL2 39798cd7f5bSHawking Zhang * 4. MQD_ADDR_LO [31:0] 39898cd7f5bSHawking Zhang * 5. MQD_ADDR_HI [31:0] 39998cd7f5bSHawking Zhang * 6. WPTR_ADDR_LO [31:0] 40098cd7f5bSHawking Zhang * 7. WPTR_ADDR_HI [31:0] 40198cd7f5bSHawking Zhang */ 40298cd7f5bSHawking Zhang /* CONTROL */ 40398cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 40498cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 40598cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 40698cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 40798cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 40898cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 40998cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 41098cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 41198cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 41298cd7f5bSHawking Zhang /* CONTROL2 */ 41398cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 41498cd7f5bSHawking Zhang # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 41598cd7f5bSHawking Zhang #define PACKET3_UNMAP_QUEUES 0xA3 41698cd7f5bSHawking Zhang /* 1. header 41798cd7f5bSHawking Zhang * 2. CONTROL 41898cd7f5bSHawking Zhang * 3. CONTROL2 41998cd7f5bSHawking Zhang * 4. CONTROL3 42098cd7f5bSHawking Zhang * 5. CONTROL4 42198cd7f5bSHawking Zhang * 6. CONTROL5 42298cd7f5bSHawking Zhang */ 42398cd7f5bSHawking Zhang /* CONTROL */ 42498cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 42598cd7f5bSHawking Zhang /* 0 - PREEMPT_QUEUES 42698cd7f5bSHawking Zhang * 1 - RESET_QUEUES 42798cd7f5bSHawking Zhang * 2 - DISABLE_PROCESS_QUEUES 42898cd7f5bSHawking Zhang * 3 - PREEMPT_QUEUES_NO_UNMAP 42998cd7f5bSHawking Zhang */ 43098cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 43198cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 43298cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 43398cd7f5bSHawking Zhang /* CONTROL2a */ 43498cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 43598cd7f5bSHawking Zhang /* CONTROL2b */ 43698cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 43798cd7f5bSHawking Zhang /* CONTROL3a */ 43898cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 43998cd7f5bSHawking Zhang /* CONTROL3b */ 44098cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 44198cd7f5bSHawking Zhang /* CONTROL4 */ 44298cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 44398cd7f5bSHawking Zhang /* CONTROL5 */ 44498cd7f5bSHawking Zhang # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 44598cd7f5bSHawking Zhang #define PACKET3_QUERY_STATUS 0xA4 44698cd7f5bSHawking Zhang /* 1. header 44798cd7f5bSHawking Zhang * 2. CONTROL 44898cd7f5bSHawking Zhang * 3. CONTROL2 44998cd7f5bSHawking Zhang * 4. ADDR_LO [31:0] 45098cd7f5bSHawking Zhang * 5. ADDR_HI [31:0] 45198cd7f5bSHawking Zhang * 6. DATA_LO [31:0] 45298cd7f5bSHawking Zhang * 7. DATA_HI [31:0] 45398cd7f5bSHawking Zhang */ 45498cd7f5bSHawking Zhang /* CONTROL */ 45598cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 45698cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 45798cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 45898cd7f5bSHawking Zhang /* CONTROL2a */ 45998cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 46098cd7f5bSHawking Zhang /* CONTROL2b */ 46198cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 46298cd7f5bSHawking Zhang # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 46398cd7f5bSHawking Zhang #define PACKET3_RUN_LIST 0xA5 46498cd7f5bSHawking Zhang #define PACKET3_MAP_PROCESS_VM 0xA6 465*46c1282eSChristian König /* GFX11 */ 466*46c1282eSChristian König #define PACKET3_SET_Q_PREEMPTION_MODE 0xF0 467*46c1282eSChristian König # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) 468*46c1282eSChristian König # define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0) 46998cd7f5bSHawking Zhang 47098cd7f5bSHawking Zhang #endif 471